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HT56R67/HT56R668/HT56R678 TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * Dual Serial Interfaces: SPI and I2C * LCD and LED driver function * 4 operating modes: normal, slow, idle and sleep * 8-channel 12-bit resolution A/D converter * 4-channel 12-bit PWM outputs * Low voltage reset function: 2.1V, 3.15V, 4.2V * Low voltage detect function: 2.2V, 3.3V, 4.4V * Bit manipulation instruction * Table read instructions * 63 powerful instructions * Up to 0.33ms instruction cycle with 12MHz system
fSYS=100kHz: 2.2V~5.5V fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.0V~5.5V fSYS=12MHz: 4.5V~5.5V
* Operating current:
fSYS=1MHz at 3V, 170mA, typ.
* OTP Program Memory: 16K16 ~ 32K16 * RAM Data Memory: 23048 * 24 to 32 bidirectional I/O lines * TinyPower technology for low power operation * Three pin-shared external interrupts lines * Multiple programmable Timer/Event Counters
clock at VDD=5V
* Multiple level subroutine nesting * All instructions executed in one or two machine
with overflow interrupt and 7-stage prescaler
* External Crystal, RC and 32768 XTAL oscillators * Fully integrated RC 32kHz oscillator * Externally supplied system clock option * Watchdog Timer function * PFD/Buzzer for audio frequency generation
cycles
* Power down and wake-up functions to reduce power
consumption
* Wide range of available package types
General Description
These TinyPowerTM A/D Type with LCD 8-bit high performance RISC architecture microcontrollers are specifically, designed for applications that interface directly to analog signals and which require an LCD or LED interface. The devices include an integrated multi-channel Analog to Digital Converter, Pulse Width Modulation outputs and an LCD/LED driver. With their fully integrated SPI and I2C functions, designers are provided with a means of easy communication with external peripheral hardware. The benefits of integrated A/D, LCD, and PWM functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appliance and industrial application areas. Some of these products could include electronic metering, environmental monitoring, handheld instruments, electronically controlled tools, motor driving in addition to many others. The unique Holtek TinyPower technology also gives the devices extremely low current consumption characteristics, an extremely important consideration in the present trend for low power battery powered applications. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applications require a minimum of external components.
Rev. 1.10
1
September 14, 2009
HT56R67/HT56R668/HT56R678
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, stack capacity and package types. The following table summarises the main features of each device. Part No. VDD Program Data Memory Memory Timer I/O LCD 8-bit 16-bit 32 484 or 493 6416 or 728 3 1 12-bit8 12-bit4 12 52QFP, 64LQFP, 100QFP 100QFP, 128QFP A/D PWM Stack Package
HT56R67 HT56R668 HT56R678 Note:
2.2V~ 5.5V 2.2V~ 5.5V
32K16 16K16
23048
23048 32K16
24
3
1
12-bit8
12-bit4
12
1. The devices are only available in OTP versions. 2. For devices that exist in more than one package formats, the table reflects the situation for the larger package.
Block Diagram
Low V o lta g e D e te c t Low V o lta g e R eset OTP P r o g r a m m in g C ir c u itr y 8 - b it R IS C MCU C o re W a tc h d o g T im e r W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r E x te rn a l R C /C ry s ta l O s c illa to r S ta c k In te rn a l R C O s c illa to r E x te rn a l R T C O s c illa to r
I/O P o rts
OTP P ro g ra m M e m o ry
RAM D a ta M e m o ry
A /D C o n v e rte r L C D /L E D D r iv e r I2C /S P I T im e r s P r o g r a m m a b le F re q u e n c y G e n e ra to r
PW M G e n e ra to r
Rev. 1.10
2
September 14, 2009
HT56R67/HT56R668/HT56R678
Pin Assignment
SEG7 SEG6 SEG5 OSC4 OSC3 VDD OSC2 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 2 P A 5 /T M R 3 PA6 S E G 1 0 /S D O SEG9 OSC4 OSC3 VDD OSC2 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 2 52515049484746454443424140 1 6 0 1 2 3 4 S 0 1 2 5 8 7 9 10 11 12 13 14151617181920212223242526 6 5 H T56R 67 5 2 Q F P -A 7 3 4 2 PB0 PB1 PB2 PB3 PB4 PB5 PD PD PD PD P P PD PD PA /A N /A N /A N /A N /A N /A N VS 0 /P W M 1 /P W M 2 /P W M 3 /P W M D 4 /IN T D 5 /IN T 6 /T M R 7 /T M R S 0 1 2 3 0 1 0 1 9 7 0 1 2 3 4 5 7 8 10 11 12 13 14 15 16 17181920212223242526272829303132 6 H T56R 67 6 4 L Q F P -A 5 4 3 2 1
64636261605958575655545352515049
P A 5 /T M R PA PA P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N VS P D 0 /P W M P D 1 /P W M P D 2 /P W M
3
39 38 37 36 35 34 33 32 31 30 29 28 27
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
1 1 /S 1 2 /S 1 3 /S 1 4 /P 1 5 /P 16 17 18 19 20 21 22 23
D I/S D A CK CS CLK IN T
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 9
8 1 0 /S 1 1 /S 1 2 /S 1 3 /S 1 4 /P 1 5 /P 16 17 18 19 20 21 22 23 DO D I/S D A C K /S C L CS CLK IN T
SEG SEG SEG COM COM COM COM V1 VMA VLC PD6 PD5 PD4 X D1 /T M R 0 /IN T 1 /IN T 0 24 25 26 3 /S E G 4 8 3
1
SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 VLC V1 VMA VLC
0
1
P A 5 /T M R PA PA PC PC PC PC P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N P B 6 /A N P B 7 /A N VS AVS P D 0 /P W M P D 1 /P W M P D 2 /P W M P D 3 /P W M P D 4 /IN T P D 5 /IN T P D 6 /T M R P D 7 /T M R PC PC PC PC VLCD S
2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 2
X D1 SEG 45 SEG 44 SEG 43 SEG 42 SEG 41 SEG 40 SEG 39 OSC4 OSC3 VDD VREF AVDD OSC2 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 2
80 79 78
D2 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
24 25 26 27 28 29 3 /S E G 4 8 2
0 46 47 0 1 2 3 4 5 6 7 8 9 1 0 /S 1 1 /S 1 2 /S 1 3 /S 1 4 /P 1 5 /P 16 17 18 19 20 21 22 23 24 25 26 27
1
6 7 4 5 6 7 0 1 2 3 4 5 6 S 0 2 3 0 1 0 1 0 1 2 3 1 1 7
9 8 7 6 5 4 3
77 76 75 74 73 72 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 71 70 69 68 67
DO
H T56R 67 1 0 0 Q F P -A
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D I/S D A C K /S C L CS CLK IN T
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 VLC V1 VMA D2 28 29 30 31 32 33 34 35 36 37 38 3 /S E G 4 8 2 X 0 1
Rev. 1.10
3
September 14, 2009
HT56R67/HT56R668/HT56R678
SEG8 SEG7 SEG6 P IN T /S E G 5 P C L K /S E G 4 S C S /S E G 3 S C K /S C L /S E G 2 S D I/S D A /S E G 1 S D O /S E G 0 OSC4 OSC3 VDD OSC2 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 2
1 100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81 2 3 4 80 79 78 77 5 76 6 75 7 74 8 73 9 72 10 71 70 69 68 11
P A 5 /T M R PA PA P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N P B 6 /A N P B 7 /A N VS P D 0 /P W M P D 1 /P W M P D 2 /P W M P D 3 /P W M P D 4 /IN T P D 5 /IN T P D 6 /T M R VLC COM COM COM COM COM COM COM COM C O M 1 0 /S E G 6 C O M 1 1 /S E G 6 D
6 7 0 1 2 3 4 5 6 S 0 1 2 0 1 0 0 1 2 3 4 5 6 7 3 7
3
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
H T56R 668 H T56R 678 1 0 0 Q F P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
9 8
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
51
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
9
10 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 47
P A 5 /T M R PA PA N N N N P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N P B 6 /A N P B 7 /A N VS AVS P D 0 /P W M P D 1 /P W M P D 2 /P W M P D 3 /P W M P D 4 /IN T P D 5 /IN T P D 6 /T M R P D 7 /T M R N N VLC COM COM COM COM COM COM COM COM C O M 8 /S E G 7 C O M 9 /S E G 7 D
6 C C C C 0 1 2 3 4 5 6 S S 0 1 2 3 0 0 C C 0 1 2 3 4 5 6 7 1 0 1 1 7 7
3
1 2 3 4 5 6 7 8 9
128 127126 125124 123122121120119118117 116115114113112111110109108107106105104 103 102 101 100 99 98 97 96 95 94 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM 48 49 50 51 52 53 54 55 56 57 56 59 60 61 62 63 1 5 /S 1 4 /S 1 3 /S 1 2 /S EG6 EG6 EG6 EG6 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 P IN T /S E G 5 P C L K /S E G 4 S C S /S E G 3 S C K /S C L /S E G 2 S D I/S D A /S E G 1 S D O /S E G 0 OSC4 OSC3 VDD VREF AVDD OSC2 4 OSC1 5 RES 6 P A 0 /B Z 7 P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 2 H T56R 668 H T56R 678 1 2 8 Q F P -A SEG SEG SEG NC NC NC NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC NC 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE CO CO CO CO CO CO G4 G6 G4 G4 G4 G4 G5 G5 G5 G5 G5 G5 G5 G5 G5 G5 G6 G6 G6 G6 M1 M1 M1 M1 M1 M1 3 2 1 0 9 8 7 6 5 4 3 5 /S 4 /S 3 /S 2 /S 1 /S 0 /S EG EG EG EG EG EG 64 65 66 67 68 69 2 1 0 9 6 7 6 5 4
Rev. 1.10
4
September 14, 2009
HT56R67/HT56R668/HT56R678
Pin Description
The following table depicts the pins common to all devices. Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4/TMR2 PA5/TMR3 PA6~PA7 I/O Configuration Option Description Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input using the PAWU register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected to each pin using the PAPU register. Pins PA0, PA1, PA3, PA4 and PA5 are shared with BZ, BZ, PFD, TMR2 and TMR3 respectively, the function of which is chosen via configuration option. Pins PA0~PA3 can also be setup as open drain pins using the MISC register. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected to each pin using the PBPU register. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor selections are disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected to each pin using the PDPU register. The PWM outputs, PWM0~PWM3, are pin shared with pins PD0~PD3, the function of which is chosen using the PWM registers. Pins PD4~PD7 are pin-shared with INT0, INT1, TMR0 and TMR1 respectively. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. EC is external clock mode, we can input clock source directly to OSC1 pin. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator to form a real time clock for fSUB. This 32768Hz crystal is disabled/enabled by configuration option. A/D reference voltage input pin Schmitt Trigger reset input. Active low Positive power supply Negative power supply, ground Analog positive power supply Analog negative power supply, ground
I/O
BZ/BZ PFD
PB0/AN0~ PB7/AN7
I/O
3/4
PD0/PWM0~ PD3/PWM3 PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1
I/O
3/4
OSC1 OSC2
I O
Crystal or RC or EC
OSC3 OSC4 VREF RES VDD VSS AVDD AVSS
I O I I 3/4 3/4 3/4 3/4
32768Hz 3/4 3/4 3/4 3/4 3/4 3/4
Rev. 1.10
5
September 14, 2009
HT56R67/HT56R668/HT56R678
The following tables depict the device dependent pins. Pin Name HT56R67 PC0~PC7 VMAX VLCD1/VLCD2/V1, C1, C2 I/O I 3/4 3/4 3/4 3/4 Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by PCPU register control bit) IC maximum voltage, connect to VDD, VLCD1 or V1 LCD Voltage pump pins for C-type biasing. For R-type biasing only pin VLCD1 are used. SEG0~SEG47 are LCD driver outputs for LCD panel segments. SEG10 is pin-shared with the SPI bus data output line, SDO. SEG11 is pin-shared with the SPI bus data input line, SDI and the I2C Bus data line SDA. SEG12 is pin-shared with the SPI bus clock line, SCK and the I2C Bus clock line SCL. SEG13 is pin-shared with the SPI bus select line, SCS. SEG14 is pin-shared with the Peripheral Clock line, PCLK. SEG15 is pin-shared with the Peripheral Interrupt line, PINT. The SEG0~SEG23 lines can be can be chosen to be either segment drivers or CMOS outputs using control bits in the LCD control registers. COM0~COM2 are the LCD common outputs. A bit in the LCD Control Register determines if pin COM3/SEG48 is configured as a segment driver or as a common output driver. I/O Configuration Option Description
SEG0~SEG9 SEG10/SDO SEG11/SDI/SDA SEG12/SCK/SCL SEG13/SCS SEG14/PCLK SEG15/PINT SEG16~SEG47
O O I/O I/O I/O O I/O O
SIM PINT
COM0~COM2 COM3/SEG48
O
3/4
HT56R668/HT56R678 VLCD SEG0/SDO SEG1/SDI/SDA SEG2/SCK/SCL SEG3/SCS SEG4/PCLK SEG5/PINT SEG6~SEG63 COM15/SEG64~ COM8/SEG71 COM0~COM7 Note: I O I/O I/O I/O O I/O O O 3/4 LCD bias pin - must less than or equal to VDD SEG0~SEG63 are LCD driver outputs for LCD panel segments. SEG0 is pin-shared with the SPI bus data output line, SDO. SEG1 is pin-shared with the SPI bus data input line, SDI and the I2C Bus data line SDA. SEG2 is pin-shared with the SPI bus clock line, SCK and the I2C Bus clock line SCL. SEG3 is pin-shared with the SPI bus select line, SCS. SEG4 is pin-shared with the Peripheral Clock line, PCLK. SEG5 is pin-shared with the Peripheral Interrupt line, PINT. The SEG0~SEG23 lines can be can be chosen to be either segment drivers or CMOS outputs using control bits in the LCD control registers. COM0~COM7 are the LCD common outputs.
SIM PINT
O
3/4
The Pin Description tables represents the largest package type available, therefore some of the pins and functions may not be available on smaller package types.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ................................................................80mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total..............................................................-80mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
6
September 14, 2009
HT56R67/HT56R668/HT56R678
D.C. Characteristics
HT56R67 Test Conditions Symbol Parameter VDD Conditions fSYS=4MHz VDD Operating Voltage 3/4 fSYS=8MHz fSYS=12MHz AVDD IDD1 Analog Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (EC Mode, Filter On) Operating Current (EC Mode, Filter Off) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) Standby Current ( Sleep) (fSYS, fSUB, fS, fLCD, fWDT=off) 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 5V 5V 3V No load, fSYS=fSLOW=500kHz 5V 3V No load, fSYS=fSLOW=1MHz 5V 3V No load, fSYS=fSLOW=2MHz 5V 3V No load, fSYS=fSLOW=1MHz 5V 3V No load, fSYS=fSLOW=2MHz 5V 3V No load, fSYS=fSLOW=4MHz 5V 3V 5V No load, system HALT, WDT off No load, system HALT, WDT on No load, fSYS=fM=8MHz No load, fSYS=fM=12MHz No load, fSYS=fM=4MHz No load, fSYS=fM=4MHz (note 5) No load, fSYS=fM=4MHz No load, fSYS=fM=2MHz VREF=AVDD No load, fSYS=fM=1MHz 2.2 3.0 4.5 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 170 380 240 490 440 900 380 720 370 680 1.8 2.6 150 340 180 400 270 560 240 540 320 680 500 1000 0.2 0.3 2 3 5.5 5.5 5.5 5.0 250 570 360 730 660 1350 570 1080 550 1020 2.7 4.0 220 510 270 600 400 840 360 810 480 1020 750 1500 1.0 2.0 4 5 V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
IDD2
IDD3
IDD4
IDD5
IDD6 IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
ISTB1
ISTB2
Standby Current ( Sleep) 3V (f SYS , f LCD , f WDT =f SUB =32768Hz 5V (note 1) or 32K_INT RC OSC)
Rev. 1.10
7
September 14, 2009
HT56R67/HT56R668/HT56R678
Test Conditions Symbol Parameter VDD Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K_INT RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K_INT RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K_INT RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K_INT RC OSC) Standby Current ( Idle) (fSYS=on, fSYS=fM=4MHz, fWDT, fLCD=off, fS (note 3)=fSUB=32768Hz (note 1) or 32K_INT RC OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 VLVR Low Voltage Reset Voltage 3/4 3/4 3/4 VLVD Low Voltage Detector Voltage 3/4 3/4 IOL1 3V I/O Port Sink Current 5V IOH1 3V I/O Port Source Current 5V IOL2 LCD Common and Segment Current LCD Common and Segment Current Pull-high Resistance for I/O Ports 5V 3V 5V 3V 5V 3V 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD Conditions No load, system HALT, WDT off, LCD on (note 2), 1/2 bias, C type, VLCD1=VDD No load, system HALT, WDT off, LCD on (note 2), 1/3 bias, C type, VLCD1=3V No load, system HALT, WDT off, LCD on (note 2), R type, VLCD1=VDD, 1/2 bias (RBIAS=400kW) No load, system HALT, WDT off, LCD on (note 2), R type, VLCD1=VDD, 1/3 bias (RBIAS=600kW) No load, system HALT, WDT off, LCD off, SPI or I2C on, PCLK on, PCLK=fSYS/8 3/4 3/4 3/4 3/4 Configuration option: 2.1V Configuration option: 3.15V Configuration option: 4.2V Configuration option: 2.2V Configuration option: 3.3V Configuration option: 4.4V VOL=0.1VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 1.98 2.98 3.98 2.08 3.12 4.12 6 10 -2 -5 210 350 -80 -180 20 10 3 4 3 4 10 18 10 16 150 5 6 5 6 15 27 15 24 250 mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V mA mA mA mA mA mA mA mA kW kW Min. Typ. Max. Unit
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
350 3/4 3/4 3/4 3/4 2.1 3.15 4.2 2.2 3.3 4.4 12 25 -4 -8 420 700 -160 -360 60 30
550 0.3VDD VDD 0.4VDD VDD 2.22 3.32 4.42 2.32 3.50 4.70 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50
VIL1 VIH1 VIL2 VIH2
IOH2
RPH
Rev. 1.10
8
September 14, 2009
HT56R67/HT56R668/HT56R678
Note: 1. 32768Hz is in slow start mode (RTCC.4=1) for the D.C. current measurement. 2. LCD waveform is in Type A condition. 3. fS is the internal clock for the Buzzer, RTC Interrupt, Time Base Interrupt and the WDT. 4. Both Timer/Event Counters are off. Timer filter is disabled for all test conditions. 5. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests. HT56R668/HT56R678 Test Conditions Symbol Parameter VDD Conditions fSYS=4MHz VDD Operating Voltage 3/4 fSYS=8MHz fSYS=12MHz AVDD IDD1 Analog Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (EC Mode, Filter On) Operating Current (EC Mode, Filter Off) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 5V 5V 3V No load, fSYS=fSLOW=500kHz 5V 3V No load, fSYS=fSLOW=1MHz 5V 3V No load, fSYS=fSLOW=2MHz 5V 3V No load, fSYS=fSLOW=1MHz 5V 3V 5V 3V 5V No load, fSYS=fSLOW=4MHz No load, fSYS=fSLOW=2MHz No load, fSYS=fM=8MHz No load, fSYS=fM=12MHz No load, fSYS=fM=4MHz No load, fSYS=fM=4MHz (note 5) No load, fSYS=fM=4MHz No load, fSYS=fM=2MHz VREF=AVDD No load, fSYS=fM=1MHz 2.2 3.0 4.5 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 170 380 240 490 440 900 380 720 370 680 1.8 2.6 150 340 180 400 270 560 240 540 320 680 500 1000 5.5 5.5 5.5 5.0 250 570 360 730 660 1350 570 1080 550 1020 2.7 4.0 220 510 270 600 400 840 360 810 480 1020 750 1500 V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
IDD2
IDD3
IDD4
IDD5
IDD6 IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
Rev. 1.10
9
September 14, 2009
HT56R67/HT56R668/HT56R678
Test Conditions Symbol Parameter VDD ISTB1 Standby Current ( Sleep) (fSYS, fSUB, fS, fLCD, fWDT=off) Standby Current ( Sleep) (fSYS, fLCD, fWDT=fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS, fWDT=off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Standby Current ( Idle) (fSYS On, fSYS=fM=4MHz, fWDT, fLCD off; fS (note 3)= fSUB=32768Hz (note 1) or 32K RC OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 VLVR Low Voltage Reset Voltage 3/4 3/4 3/4 VLVD Low Voltage Detector Voltage 3/4 3/4 Conditions No load, system HALT, LCD off, WD off No load, system HALT, LCD off, WD off No load, system HALT, WDT off, LCD on (note 2), 1/5 bias (RBIAS=1MW), VLCD=VDD No load, system HALT, WDT off, LCD on (note 2), 1/4 bias (RBIAS=800kW), VLCD=VDD No load, system HALT, WDT off, LCD on (note 2), 1/3 bias (RBIAS=600kW), VLCD=VDD No load, system HALT, WDT off, LCD on (note 2), 1/5 bias (RBIAS=100kW), VLCD=VDD No load, system HALT, WDT off, LCD on (note 2), 1/4 bias (RBIAS=80kW), VLCD=VDD No load, system HALT, WDT off, LCD on (note 2), 1/3 bias (RBIAS=60kW), VLCD=VDD No load, system HALT, LCD off, WDT off, SPI or I2C On, PCLK On, PCLK=fSYS/8 3/4 3/4 3/4 3/4 Configuration option: 4.2V Configuration option: 3.15V Configuration option: 2.1V Configuration option: 2.2V Configuration option: 3.3V Configuration option: 4.4V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 3.98 2.98 1.98 2.08 3.12 4.12 0.2 0.3 2 3 6 10 6 10 8 12 26 44 32 54 44 70 150 1.0 2.0 4 5 10 15 10 15 12 16 39 66 48 81 66 105 250 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V Min. Typ. Max. Unit
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
ISTB8
ISTB9
350 3/4 3/4 3/4 3/4 4.2 3.15 2.1 2.2 3.3 4.4
550 0.3VDD VDD 0.4VDD VDD 4.42 3.32 2.22 2.32 3.50 4.70
VIL1 VIH1 VIL2 VIH2
Rev. 1.10
10
September 14, 2009
HT56R67/HT56R668/HT56R678
Test Conditions Symbol Parameter VDD IOL1 I/O Port Sink Current (PA, PB, PD; SEG, COM Level or LED Output) I/O Port Source Current (PA, PB, PD; SEG, COM Level or LED Output) LCD Common and Segment Current LCD Common and Segment Current Pull-high Resistance for I/O Ports 3V VOL=0.1VDD 5V 3V VOH=0.9VDD 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 VOH=0.9VDD VOL=0.1VDD 10 -2 -5 210 350 -80 -180 20 10 25 -4 -8 420 700 -160 -360 60 30 Conditions 6 12 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 mA mA mA mA mA mA mA mA kW kW Min. Typ. Max. Unit
IOH1
IOL2
IOH2
RPH Note:
1. 32768Hz is slow start mode (RTCC.4=1) in D.C. current measurement. 2. LCD waveform is in Type A condition. 3. fS is internal clock for Buzzer, RTC, Time base and WDT. 4. Timer0/1 off. Timer filter disable in all test condition. 5. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests.
A.C. Characteristics
Test Conditions Symbol Parameter VDD System Clock (Crystal OSC, RC OSC) RTC Frequency Timer I/P Frequency (TMR0/TMR1) 32K RC Oscillator External Reset Low Pulse Width Low Voltage Reset Time System Start-up Timer Period System Start-up Timer Period for XTAL or RTC oscillator System Start-up Timer Period for External RC or External Clock Interrupt Pulse Width *tSYS=1/fSYS Conditions 2.2V~5.5V fSYS 3/4 3.0V~5.5V 4.5V~5.5V fRTCOSC 3/4 2.2V~5.5V fTIMER 3/4 3.0V~5.5V 4.5V~5.5V fRC32K tRES tLVR tSST1 tSST2 3/4 3/4 3/4 3/4 3/4 Power-on Wake-up from Power Down Mode Wake-up from Power Down Mode 3/4 2.2V~5.5V, After Trim 3/4 3/4 3/4 100 100 100 3/4 0 0 0 28.8 1 0.1 3/4 3/4 3/4 3/4 3/4 32768 3/4 3/4 3/4 32.0 3/4 0.4 1024 1024 4000 8000 12000 3/4 4000 8000 12000 35.2 3/4 0.6 3/4 3/4 Min. Typ. Max.
Ta=25C Unit kHz kHz kHz Hz kHz kHz kHz kHz ms ms tSYS* tSYS*
tSST3 tINT Note:
3/4 3/4
3/4 1
1 3/4
2 3/4
tSYS* ms
Rev. 1.10
11
September 14, 2009
HT56R67/HT56R668/HT56R678
ADC Characteristics
HT56R67 Test Conditions Symbol Parameter VDD VAD A/D Input Voltage A/D Input Reference Voltage Range A/C Differential Non-Linearity ADC Integral Non-Linearity Additional Power Consumption if A/D Converter is Used A/D Clock Period A/D Conversion Time 3/4 3/4 3/4 3/4 3V 5V 3/4 3/4 Conditions 52QFP, 64LQFP 100QFP AVDD=5V AVDD=5V, VREF=AVDD, tAD=0.5ms AVDD=5V, VREF=AVDD, tAD=0.5ms 3/4 3/4 3/4 0 0 1.6 -2 -4 3/4 3/4 0.5 3/4 3/4 3/4 3/4 3/4 3/4 0.50 1.00 3/4 16 AVDD VREF AVDD+0.1 2 4 0.75 1.50 3/4 3/4 V V V LSB LSB mA mA ms tAD Ta=25C Test Conditions Symbol Parameter VDD VAD A/D Input Voltage A/D Input Reference Voltage Range A/C Differential Non-Linearity ADC Integral Non-Linearity Additional Power Consumption if A/D Converter is Used A/D Clock Period A/D Conversion Time 3/4 3/4 3/4 3/4 3V 5V 3/4 3/4 Conditions 100QFP 128QFP AVDD=5V AVDD=5V, VREF=AVDD, tAD=0.5ms AVDD=5V, VREF=AVDD, tAD=0.5ms 3/4 3/4 3/4 0 0 1.6 -2 -4 3/4 3/4 0.5 3/4 3/4 3/4 3/4 3/4 3/4 0.50 1.00 3/4 16 AVDD VREF AVDD+0.1 2 4 0.75 1.50 3/4 3/4 V V V LSB LSB mA mA ms tAD Min. Typ. Max. Unit Min. Typ. Max. Unit Ta=25C
VREF DNL INL
IADC tAD tADC
HT56R668/HT56R678
VREF DNL INL
IADC tAD tADC
Rev. 1.10
12
September 14, 2009
HT56R67/HT56R668/HT56R678
Power-on Reset Characteristics
Test Conditions Symbol VPOR RRVDD tPOR Parameter VDD VDD Start Voltage to Ensure Power-on Reset VDD raising rate to Ensure Power-on Reset Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 0.035 1 3/4 3/4 3/4 100 3/4 3/4 mV V/ms ms Min. Typ. Max. Unit Ta=25C
V
DD
tP
OR
RR
VDD
V
POR
T im e
Rev. 1.10
13
September 14, 2009
HT56R67/HT56R668/HT56R678
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is free for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.10
14
September 14, 2009
HT56R67/HT56R668/HT56R678
Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section.
Program Counter Bits Mode b14 Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow SPI/I C Interrupt Multi-Function Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
2
b13 0 0 0 0 0 0 0
b12 0 0 0 0 0 0 0
b11 0 0 0 0 0 0 0
b10 0 0 0 0 0 0 0
b9 0 0 0 0 0 0 0
b8 0 0 0 0 0 0 0
b7 0 0 0 0 0 0 0
b6 0 0 0 0 0 0 0
b5 0 0 0 0 0 0 0
b4 0 0 0 0 1 1 1
b3 0 0 1 1 0 0 1
b2 0 1 0 1 0 1 0
b1 0 0 0 0 0 0 0
b0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
Program Counter + 2 PC14 PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 BP.6 BP.5 S14 S13 #12 S12 #11 S11 #10 S10 #9 S9 #8 S8 #7 S7 #6 S6 #5 S5 #4 S4 #3 S3 #2 S2 #1 S1 #0 S0
Program Counter Note: PC14~PC8: Current Program Counter bits @7~@0: PCL bits #12~#0: Instruction code address bits S14~S0: Stack register bits For the HT56R67/HT56R678, the Program Counter is 15 bits wide, i.e. from b14~b0. For the HT56R668, the Program Counter is 14 bits wide, i.e. from b13~b0, therefore the b12 column in the table is not applicable. BP.6, BP.5: Bank pointer bits
141312 87 P ro g ra m
BP .6 BP .5
0 C o u n te r
B a n k P o in te r (B P )
Rev. 1.10
15
September 14, 2009
HT56R67/HT56R668/HT56R678
Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m C o u n te r
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. For these device the Program Memory is an OTP type, which means it can be programmed only one time. By using the appropriate programming tools, this OTP memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. Structure
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 1 2
The Program Memory has a capacity of 16K16 bits to 32K16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
This vector is used by the external interrupt 0. If the external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
This vector is used by the external interrupt 1. If the external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 00CH
This internal vector is used by the Timer/Event Counter 0. If a Timer/Event Counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full.
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Rev. 1.10
16
September 14, 2009
HT56R67/HT56R668/HT56R678
* Location 010H * Location 018H
This internal vector is used by the Timer/Event Counter 1. If a Timer/Event Counter 1 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full.
* Location 014H
This internal vector is used by the SPI/I2C interrupt. When either an SPI or I2C bus, dependent upon which one is selected, requires data transfer, the program will jump to this location and begin execution if the SPI/I2C interrupt is enabled and the stack is not full.
000H 004H 008H 00CH 010H 014H 018H 01CH 700H 7FFH 800H FFFH 1000H 1FFFH 1 6 b its N o t Im p le m e n te d In itia lis a tio n V e c to r E x te rn a l IN T 0 In te rru p t V e c to r E x te rn a l IN T 1 In te rru p t V e c to r T im e r C o u n te r 0 In te rru p t V e c to r T im e r C o u n te r 1 In te rru p t V e c to r
This internal vector is used by the Multi-function Interrupt. The Multi-function Interrupt vector is shared by several internal functions such as a Time Base overflow, a Real Time Clock overflow, an A/D converter conversion completion, an active edge appearing on the External Peripheral interrupt pin, a Timer/Event Counter 2 or a Timer/Event Counter 3 overflow. The program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the TABRDC[m] or TABRDL [m] instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The following diagram illustrates the addressing/data flow of the look-up table:
P ro g ra m C o u n te r H ig h B y te TBLP P ro g ra m M e m o ry
S P I/I2C In te rru p t V e c to r M u lti_ F u n c tio n In te rru p t V e c to r
Program Memory Structure
TBLH T a b le C o n te n ts H ig h B y te S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
Table Location Bits Instruction b14 TABRDC [m] TABRDL [m] b13 b12 b11 b10 b9 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0 PC14 PC13 PC12 PC11 PC10 PC9 1 1 1 1 1 1
Table Location Note: PC14~PC8: Current program counter bits @7~@0: Table Pointer TBLP bits For the HT56R67/HT56R678, the Table address location is 15 bits, i.e. from b14~b0. For the HT56R668, the Table address location is 14 bits, i.e. from b13~b0.
Rev. 1.10
17
September 14, 2009
HT56R67/HT56R668/HT56R678
Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT56R678. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 7F00H which refers to the start address of the last page within the 32K Program Memory of the HT56R678 microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 7F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
tempreg1 db tempreg2 db : : mov a,06h mov tblp,a : : tabrdl
? ?
; temporary register #1 ; temporary register #2
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tempreg1
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 7F06H transferred to tempreg1 and TBLH
dec tblp tabrdl tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 7F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org 7F00h dc ; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
Rev. 1.10
18
September 14, 2009
HT56R67/HT56R668/HT56R678
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into three sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The third area is reserved for the LCD Memory. This special area of Data Memory is mapped directly to the LCD display so data written into this memory area will directly affect the displayed data. The addresses of the LCD Memory area overlap those in the General Purpose Data Memory area. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. Structure The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide RAM. The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. Bank Number SPDM HT56R67 - 2304 Bytes GPDM SA EA SA EA SA EA SA EA 40H 40H 40H 40H 40H 40H 40H 40H 40H 40H 0 1 2 3 4 5 6 The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. The LCD Memory is mapped into Bank 1. Banks 2 to 12 contain only General Purpose Data Memory for those devices with larger Data Memory capacities. As the Special Purpose Data Memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location.
00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry FFH
Bank 1 LC D M e m o ry
Bank 0 Bank 2 Bank 3 Bank 12
Data Memory Structure
7
8
9
10
11
12
Common 00H Common 3FH 40H 40H 40H 40H 40H 40H 40H 40H
FFH 70H FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH Common 00H Common 3FH 40H 40H 40H 40H 40H 40H 40H 40H
HT56R668 HT56R678 - 2304 Bytes
SPDM
GPDM
FFH BFH FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH Data Memory Content
Note:
SPDM: Special Purpose Data Memory GPDM: General Purpose Data Memory SA: Start Address EA: End Address x: Not implemented
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General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. For devices with larger Data Memory capacities, the General Purpose Data Memory, in addition to being located in Bank 0, is also stored in Banks 2 to 12, the actual number of banks present depends upon the device selected. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both read and write type but some are protected and are read only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H. The Special Function registers are mapped into all banks and can therefore be accessed from any bank location. Display Memory The data to be displayed on the LCD or LED display is stored in an area of fully accessible Data Memory. By writing to this area of RAM, the display output can be directly controlled by the application program. As this Memory exists in Bank 1, but have addresses which map into the General Purpose Data Memory, it is necessary to first ensure that the Bank Pointer is set to the value 01H before accessing the Display Memory. The Display Memory can only be accessed indirectly using the Memory Pointer MP1 and the indirect addressing register IAR1. When the Bank Pointer is set to Bank 1 to access the Display Memory, if any addresses with a value less than 40H are read, the Special Purpose Memory in Bank 0 will be accessed. Also, if the Bank Pointer is set to Bank 1, if any addresses higher than the last address in Bank 1 are read, then a value of 00H will be returned.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH H T56R 67 R0 P0 R1 P1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M 0L PW M 0H PW M 1L PW M 1H IN T C 1 P P P PW PW PW PW AD AD AD AC CLK PA PA PB PC PD IN T E M2 M2 M3 M3 RL RH CR SR MO WU PU PU PU PU DG H H L L IA M IA M H T56R 668 H T56R 678 IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PD PDC W M 0L W M 0H W M 1L W M 1H IN T C 1 P M2 M2 M3 M3 RL RH CR SR MO WU PU PU H H L L
D
PW PW PW PW AD AD AD AC CLK PA PA PB E
D
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special Rev. 1.10 20
LCDCTRL LCDO UT1 LCDO UT2 M IS C M F IC 0 M F IC 1 S IM C T L 0 S IM C T L 1 S IM D R S IM A R /S IM C T L 2 TM R2 TM R2C TM R3 TM R3C
PDPU IN T E D G E LED CTRL LCDCTRL LCDO UT1 LCDO UT2 M IS C M F IC 0 M F IC 1 S IM C T L 0 S IM C T L 1 S IM D R S IM A R /S IM C T L 2 TM R2 TM R2C TM R3 TM R3C
: U n u s e d R e a d a s "0 0 "
Special Purpose Data Memory
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HT56R67/HT56R668/HT56R678
function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Registers - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4.
data .section data adres1 db ? adres2 db ? Adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp a,04h block,a a,offset adres1 mp0,a IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared
continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
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Bank Pointer - BP The Data Memory is divided several banks, the total number of which depends upon the device chosen. Selecting the required Data Memory area is achieved using the Bank Pointer. If data in Bank 0 is to be accessed, then the BP register must be loaded with the value 00H, while if data in Bank 1 is to be accessed, then the BP register must be loaded with the value 01H, and so on. The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory lob7 BP6 BP5 BP3 BP2 BP1 b0 BP0
cation, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
B P R e g is te r BP 00 00 00 11 3~BP0 00 01 10~1100 01~1111 Ba Ba Ba Da nk nk nk ta 0o 1( 2~ me D a ta fgene LC D m 12 ge m o ry n M em or ra l d a ta e m o ry ) n e ra l d a o t im p le y m e m o ry ta m e m o ry m e n te d
R e s e r v e d fo r fu tu r e u s e , w r ite " 0 " o n ly . Im p le m e n te d a s 8 K R O M x 4 s e le c tio n b it
R e s e r v e d fo r fu tu r e u s e , w r ite " 0 " o n ly .
Bank Pointer Rev. 1.10 22 September 14, 2009
HT56R67/HT56R668/HT56R678
b7 TO PDF OV Z AC b0 C S T A T U S R e g is te r Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
registers can also be preloaded with fixed data to allow different time intervals to be setup. The associated control registers, TMR0C, TMR1C, TMR2C and TMR3C contain the setup information for these timers, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Pulse Width Modulator Registers The devices contain multiple Pulse Width Modulator outputs each with their own related independent control register pair, known as PWM0L/PWM0H, PWM1L/PWM1H, PWM2L/PWM2H and PWM3L/PWM3H. The 12-bit contents of each register pair, which defines the duty cycle value for the modulation cycle of the Pulse Width Modulator, along with an enable bit are contained in these register pairs.
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Registers These 8-bit registers, INTC0, INTC1, MFIC, MFIC0, MFIC1 and INTEDGE, control the operation of the device interrupt functions. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within the INTC0 register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. The INTEDGE register is used to select the active edges for the two external interrupt pins INT0 and INT1. Timer/Event Counter Registers The devices contain several internal 8-bit and 16-bit Timer/Event Counters, the actual amount depends upon which device is selected. The registers TMR0, TMR1, TMR2, TMR3 and the register pair TMR1L/TMR1H are the locations where the timer values are located. These
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A/D Converter Registers ADRL, ADRH, ADCR, ACSR The device contains a multiple channel 12-bit A/D converter. The correct operation of the A/D requires the use of two data registers and two control registers. The two data registers, a high byte data register known as ADRH, and a low byte data register known as ADRL, are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. Functions such as the A/D enable/disable, A/D channel selection and A/D clock frequency are determined using the two control registers, ADCR and ACSR. Serial Interface Registers The device contains two serial interfaces, an SPI and an I2C interface. The SIMCTL0, SIMCTL1, SIMCTL2 and SIMAR are the control registers for the Serial Interface function while the SIMDR is the data register for the Serial Interface Data. Port A Wake-up Register - PAWU All pins on Port A have a wake-up function enable a low going edge on these pins to wake-up the device when it is in a power down mode. The pins on Port A that are used to have a wake-up function are selected using this resister. Pull-High Resistors - PAPU, PBPU, PCPU, PDPU All I/O pins on Ports PA, PB, PC and PD, if setup as inputs, can be connected to an internal pull-high resistor. The pins which require a pull-high resistor to be connected are selected using these registers. Register - CLKMOD The device operates using a dual clock system whose mode is controlled using this register. The register controls functions such as the clock source, the idle mode enable and the division ratio for the slow clock. LCD/LED Registers LCDCTRL, LEDCTRL, LCDOUT1, LCDOUT2 The device contains a fully integrated LCD/LED Driver function which can be setup in various configurations allowing it to control a wide range of external LCD and LED panels. Most of these options are controlled using the LCDCTRL and LECTRL registers. As some of the LCD segment driving pins can also be setup to be used as CMOS outputs, two registers, LCDOUT1 and LCDOUT2, are used to select the required function. Miscellaneous Register - MISC The miscellaneous register is used to control two functions. The four lower bits are used for the Watchdog Timer control, while the highest four bits are used to select open drain outputs for pins PA0~PA3.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides 32 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU, PBPU, PCPU and PDPU and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into a Power Down condition which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a Power Down condition, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Port A Open Drain Function All I/O pins in the device have CMOS structures, however Port A pins PA0~PA3 can also be setup as open drain structures. This is implemented using the ODE0~ ODE3 bits in the MISC register.
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b7 ODE3 ODE2 ODE1 ODE0 W DTEN3 W DTEN2 W DTEN1 b0 W DTEN0 M IS C R e g is te r
W a tc h d o g T im e r E n a b le C o n tr o l - d e s c r ib e d e ls e w h e r e P A 0 O p e n D r a in C o n tr o l 1 : e n a b le 0 : d is a b le P A 1 O p e n D r a in C o n tr o l 1 : e n a b le 0 : d is a b le P A 2 O p e n D r a in C o n tr o l 1 : e n a b le 0 : d is a b le P A 3 O p e n D r a in C o n tr o l 1 : e n a b le 0 : d is a b le
PA0~PA3 Open Drain Control - MISC
V C o n tr o l B it
DD
D a ta B u s
D
Q CK S Q
P u ll- H ig h O p tio n
W eak P u ll- u p
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
I/O D a ta B it Q D CK Q S M U X P A o n ly
p in
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
W a k e - u p S e le c t
Generic Input/Output Structure
V C o n tr o l B it Q D CK S Q P u ll- H ig h R e g is te r S e le c t
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
A /D D a ta B it Q D CK S Q
M U X
In p u t P o rt
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r PCR2 PCR1 PCR0 T o A /D C o n v e rte r
A n a lo g In p u t S e le c to r
AC S2~ACS0
A/D Input/Output Structure Rev. 1.10 25 September 14, 2009
HT56R67/HT56R668/HT56R678
b7 P xP U 7 P xP U 1 b0 P xP U 0 PA PU ,PB PU ,PC PU ,PD PU R e g is te r
P A .0 , P B .0 , P C .0 , P D .0 P u ll- h ig h 1 : e n a b le 0 : d is a b le P A .1 , P B .1 , P C .1 , P D .1 P u ll- h ig h 1 : e n a b le 0 : d is a b le
P A .7 , P B .7 , P C .7 , P D .7 P u ll- h ig h 1 : e n a b le 0 : d is a b le
Pull-High Resistor Register - PAPU, PBPU, PCPU, PDPU I/O Port Control Registers Each I/O port has its own control register known as PAC, PBC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* External Interrupt Inputs * PFD Output
The device contains a PFD function whose single output is pin-shared with I/O pin PA3. The output function of this pin is chosen via a configuration option and remains fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the PFD configuration option has been selected.
* PWM Outputs
The device contains several PWM outputs shared with pins PD0~PD3. The PWM output functions are chosen via registers. Note that the corresponding bit of the port control register, PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the PWM registers have enabled the PWM function.
* A/D Inputs
The device contains a multi-channel A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor register remain, however if used as A/D inputs then any pull-high resistor selections associated with these pins will be automatically disconnected. I/O Pin Structures The accompanying diagrams illustrate the internal structures of some I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown.
The external interrupt pins INT0, INT1 are pin-shared with the I/O pins PD4, PD5. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC0 register must be disabled.
* External Timer Clock Input
The external timer pins TMR0, TMR1, TMR2 and TMR3 are pin-shared with I/O pins. To configure them to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set and the pin must also be setup as an input. Note that the original I/O function will remain even if the pin is setup to be used as an external timer input. Rev. 1.10 26
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Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC, PBC, PCC and PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PC and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
special considerations for proper LCD operation to occur. These devices all contain an LCD Driver function, which with their internal LCD signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. Additionally some of the devices also include LED driver circuitry which can generated the required signals to drive the COM and SEGMENT signals for LED panels. All device include a wide range of options to enable LCD and LED displays of various types to be driven. The table shows the range of options available across the device range. Part No. Duty 1/2 HT56R67 1/3 1/4 1/8 HT56R668 HT56R678 1/16 728 Driver No. 492 493 484 6416 Bias 1/2 or 1/3 1/3 or 1/4 or 1/5 Bias Type C or R Wave Type A or B
R
A or B
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
LCD Selections Note: The HT56R67 devices do not have an LED driver function. Device LED Duty Static 1/4 HT56R668 HT56R678 1/8 1/12 LED Driver No. 721 724 728 6412 6416
Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
LCD and LED Driver
For large volume applications, which incorporate an LCD in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. However, the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a custom display require many
1/16 LED Selections Note:
The and HT56R67 devices do not have an LED driver function.
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September 14, 2009
HT56R67/HT56R668/HT56R678
VMAX VLC D1
(= V L C D 1 1 .5 )
VMAX LC D P o w e r S u p p ly VLC D 1 V C1
A
V
A
LC D P o w e r S u p p ly 0 .1 m F
C1 C h a rg e Pum p C2 V1 0 .1 m F VLCD2 0 .1 m F
(= V L C D 1 )
V
B
0 .1 m F
(= V L C D 1 )
C h a rg e Pum p
C2 V1
(= V L C D 1 0 .5 V C u s e d fo r 1 /3 B ia s o n ly )
V
C
(= V L C D 1 0 .5 )
V
B
0 .1 m F VLCD2
0 .1 m F
C ty p e 1 /2 B ia s p
C
3 C h a rg e P u m
ty p e 1 /3 B ia s p
2 C h a rg e P u m
C Type Bias Voltage Levels
VMAX
(= V L C D 1 )
VMAX LCD P o w e r S u p p ly
V V
A
VLCD 1 R R R
(= V L C D 1 )
V
A
VLC D1 R
LC D P o w e r S u p p ly
(= V L C D 1 2 /3 ) (= V L C D 1 1 /3 )
B
V
C
(= V L C D 1 1 /2 )
V
B
R
L C D O n /O ff
L C D O n /O ff
R
ty p e 1 /3 B ia s
R
ty p e 1 /2 B ia s
R Type Bias Voltage Levels - HT56R67
(= V L C D )
V V
A
VLCD R R R
LCD P o w e r S u p p ly
(= V L C D 2 /3 ) (= V L C D 1 /3 )
B
V
C
L C D O n /O ff
R
ty p e 1 /3 B ia s
(= V L C D )
V V
A
VLCD R R R R
LCD P o w e r S u p p ly
V
A
VLCD R
(= V L C D )
LCD P o w e r S u p p ly
(= V L C D 4 /5 ) (= V L C D 3 /5 )
B
V
B
V
(= V L C D 3 /4 )
C
R
V
C
(= V L C D 2 /5 ) (= V L C D 1 /5 )
V
D
(= V L C D 2 /4 )
R
V
E
(= V L C D 1 /4 )
V
D
R LCD O n /O ff
R
L C D O n /O ff
R
ty p e 1 /5 B ia s
R
ty p e 1 /4 B ia s
R Type Bias Voltage Levels - HT56R668/HT56R678 Rev. 1.10 28 September 14, 2009
HT56R67/HT56R668/HT56R678
Display Memory An area of Data Memory is especially reserved for use for the LCD/LED display data. This data area is known as the Display Memory. Any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary LCD or LED driving signals. Therefore any data written into this Memory will be immediately reflected into the actual display connected to the microcontroller. As the Display Memory addresses overlap those of the General Purpose Data Memory, it s stored in its own independent Bank 1 area. The Data Memory Bank to be used is chosen by using the Bank Pointer, which is a special function register in the Data Memory, with the name, BP. To access the Display Memory therefore requires first that Bank 1 is selected by writing a value of 01H to the BP register. After this, the memory can then be accessed by using indirect addressing through the use of Memory Pointer MP1. With Bank 1 selected, then using MP1 to read or write to the memory area, starting with address 40H, will result in operations to the Display Memory. Directly addressing the Display Memory is not applicable and will result in a data access to the Bank 0 General Purpose Data Memory. The accompanying Display Memory Map diagrams shows how the internal Display Memory is mapped to the Segments and Commons of the display for the largest device, which is the HT56R678. Display Memory Maps for devices with smaller memory capacities can be extrapolated from these diagrams. The accompanying waveform diagrams show the generated waveforms for a range of duty and bias types. The huge number of permutations of available for the LCD and LED waveform types does not permit all types to be depicted.
b7 40H 41H b6 b5 b4 b3 b2 b1 b0 SEG SEG 0 1
86H 87H COM 7 COM6 COM5 COM 4 COM 3 COM 2 COM 1 COM 0
SEG SEG
70 71
HT56R678 Memory Map - 728
b7 40H 41H
b6
b5
b4
b3
b2
b1
b0 SEG SEG 0 1 80H 81H
b7
b6
b5
b4
b3
b2
b1
b0 SEG SEG 0 1
7EH 7FH COM 7 COM6 COM5 COM 4 COM 3 COM 2 COM 1 COM 0
SEG SEG
62 63
BEH BFH COM 15 COM 14 COM 13 COM 12 COM 11 COM 10 COM 9 COM 8
SEG SEG
62 63
HT56R678 Memory Map - 6416
Rev. 1.10
29
September 14, 2009
HT56R67/HT56R668/HT56R678
LCD/LED Registers Control Registers in the Data Memory, are used to control the various setup features of the LCD/LED Driver. There is one control register for the LCD function, LCDCTRL, and one for the LED function, LEDCTRL. Various bits in these registers control functions such as duty type, bias type, bias resistor selection as well as overall LCD enable and disable. The LEDSEL bit in the LEDCTRL register must be first setup to determine whether the display is an LED or LCD type. Programming this bit will determine what other options are available. The LCDEN bit in the LCDCTRL and LEDEN bit in the LEDCTRL register, which provide the overall LCD/LED enable/disable function, will only be effective when the device is in the Normal, Slow or Idle Mode. If the device is in the Sleep Mode then the display will always be disabled. Bits RSEL0 and RSEL1 in the LCDCTRL register select the internal bias resistors to supply the LCD panel with the correct bias voltages. A choice to best match the LCD panel used in the application can be selected also to minimise bias current. The TYPE bit in the same register is used to select whether Type A or Type B LCD control signals are used. Two registers, LCDOUT1 and LCDOUT2 are used to determine if the output function of display pins SEG0~ SEG23 are used as segment drivers or CMOS outputs. If used as CMOS outputs then the Display Memory is used to determine the logic level of the CMOS output pins. Note that as only two bits are used to determine t h e o u t p u t f u n c t i o n o f t h e S E G 0~ S E G 7 a n d SEG8~SEG15 pins, individual pins from these two groups of pins cannot be chosen to have either a segment or CMOS output function. The output function of pins SEG16~SEG23 can be chosen individually to be either a segment driver or a CMOS input. LCD Reset Function The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the LCDCTRL register and the Sleep function. The LCD reset signal is active high. The LCDEN signal is the inverse of the LCDEN bit in the LCDCTRL register. Reset LCD = Sleep Mode or LCDEN. LCDEN =0 and LCDEN =1 must be enabled to activate the LCDCTRL register function. LCDEN 0 0 1 1 Sleep Mode Off On Off On LCD Reset Function Reset LCD O O x O Clock Source The LCD clock source is the internal clock signal, fSUB, divided by 8, using an internal divider circuit. The fSUB internal clock is supplied by either the internal 32K_INT oscillator or the external 32768Hz oscillator, the choice of which is determined by a configuration option. For proper LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz. fSUB Clock Source Internal 32K_INT Osc. External 32768Hz Osc. LCD Clock Frequency 4kHz 4kHz
LCD Clock Source LCD Driver Output When the LEDSEL bit in the LEDCTRL register is cleared to zero, the COM and SEG lines will be setup as LCD driver pins to drive the LCD display. Only HT56R668/HT56R678 are with LEDCTRL register. The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and duty selections, are dependent upon how the LCD control bits are programmed. The Bias Type, whether C or R type is selected using a configuration option. Only HT56R67 are with R or C type selection configuration option. If the C-type of bias is used when an internal charge pump will be enabled. Note that the C-type bias is not available on the 52-pin QFP package type. The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels may cause permanent damage. For this reason the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel, which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. The requirement to limit the DC voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application LCD. These time and amplitude varying signals are automatically generated by the LCD driver circuits in the microcontroller. What is known as the duty determines the number of common lines used, which are also known as backplanes or COMs. The duty, which is chosen by a control bit to have a value of 1/2, 1/3, 1/4 etc and which equates to a COM number of 2, 3, 4 etc, therefore defines the number of time divisions within each LCD signal frame. Two types of signal generation are also provided, known as Type A and Type B, the required type is selected via the TYPE bit in the LCDCTRL register. Type B offers lower frequency signals, however lower frequencies may introduce flickering and influence display clarity. 30 September 14, 2009
Rev. 1.10
HT56R67/HT56R668/HT56R678
b7 TYPE b0 DTYC1 DTYC0 B IA S RSEL1 RSEL0 LCDEN L C D C T R L R e g is te r LCD e 1:ena 0 : d is a In th e LCD w In th e LCD RSE 0 0 1 1 LCD 1 : 1 /3 0 : 1 /2 n a b le b le b le N o rm ill b e S le e p /d is a b le c o n tr o l a l, S lo w o r Id le m o d e o n /o ff a c c o r d in g to " L C D E N " = 1 /0 m o d e th e L C D is a lw a y s o ff B ia s 0kW 0kW 0kW kW 1 /2 B ia s 40 20 67 34 0kW 0kW kW kW
b ia s r e s is to r s e le c t L1 R SEL0 1 /3 60 0 30 1 10 0 1 50 B ia s B ia s B ia s
N o t im p le m e n te d , r e a d a s " 0 " L C D D u ty DTYC1 0 0 1 1 DTYC0 0 1 1 1 0 1 1 r LC D Type A orB 1:Type B 0:Type A
/2 d u /3 d u /4 d u e s e rv
ty ty ty ed
LCD Control Register - LCDCTRL - HT56R67
b7 TYPE
b0 DTYC B IA S 1 B IA S 0 RSEL1 RSEL0 LCDEN L C D C T R L R e g is te r LCD 1:e 0:d In N LCD In S e n a b le n a b le is a b le o r m a l, S w ill b e le e p m o /d is a b le c o n tr o l: d e fa u lt v a lu e " 0 " lo w , Id le m o d e o n /o ff a c c o r d in g to " L C D E N " = 1 /0 d e L C D is a lw a y s o ff s is to r s e le SEL0 1 x 1 0 1 1 5 ct /5 B ia s 000kW 00kW kW B ia s 1 /3 1 /4 1 /5 Re 1 /4 B ia s 800kW 80kW 4kW 1 /3 B ia s 600kW 60kW 3kW
L C D b ia s r e R SEL1 R 0 1 1
D e fin e L C D b ia s B IA S 1 B IA S 0 0 0 1 0 0 1 1 1 D e fin e L C D d u ty 0 : 1 /8 d u ty 1 : 1 /1 6 d u ty
00: 01: 10: 11:
B ia B ia B ia s e rv s
s s ed
N o t im p le m e n te d , r e a d a s " 0 " LC D Type A orB 0:Type A 1:Type B
LCD Control Register - LCDCTRL - HT56R668/HT56R678
Rev. 1.10
31
September 14, 2009
HT56R67/HT56R668/HT56R678
b7 DTYE2 DTYE1 DTYE0 SEGP COMP LEDEN b0 LEDSEL L E D C T R L R e g is te r S e le c t L C D 0:LC D 1:LED LED 0:d 1:e In N LED In S e n a b le is a b le n a b le o r m a l, S w ill b e le e p m o orLED
/d is a b le c o n tr o l: d e fa u lt v a lu e " 0 " lo w , Id le m o d e o n /o ff a c c o r d in g to " L E D E N " = 1 /0 d e L E D is a lw a y s o ff
S e le c t C O M p o la r ity 0 : lo w a c tiv e 1 : h ig h a c tiv e S e le c t S E G p o la r ity 0 : lo w a c tiv e 1 : h ig h a c tiv e D e fin e L E D d u ty DTYE2 DTYE1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 DTYE0 0 1 0 1 0 1 0 1
s ta 1 /4 1 /8 1 /8 1 /1 1 /1 1 /1 1 /1
tic d d d 2 2 6 6
u ty u ty u ty d u ty d u ty d u ty d u ty
N o t im p le m e n te d , r e a d a s " 0 "
LED Control Register - LEDCTRL - HT56R668/HT56R678
b7 LCDO 8
b0 LCDO 0
L C D O U T 1 R e g is te r S E G 0 ~ S E G 7 s e g m e n t o r C M O S o u tp u t 1 : C M O S o u tp u t 0 : S E G o u tp u t S E G 8 ~ S E G 1 5 s e g m e n t o r C M O S o u tp u t 1 : C M O S o u tp u t 0 : S E G o u tp u t N o t im p le m e n te d , r e a d a s " 0 "
LCD Output Control Register - LCDOUT1
b7 LCDO 23 LCDO 22 LCDO 21 LCDO 20 LCDO 19 LCDO 18 LCDO 17
b0 LCDO 16
L C D O U T 2 R e g is te r S E G 1 6 ~ S E G 2 3 s e g m e n t o r C M O S o u tp u t 1 : C M O S o u tp u t 0 : S E G o u tp u t
LCD Output Control Register - LCDOUT2
Rev. 1.10
32
September 14, 2009
HT56R67/HT56R668/HT56R678
LED Driver Output The LED driver uses the COM and SEG lines to drive the LED display. The number of COM and SEG outputs supplied by the LED driver, as well as its biasing and duty selections, are dependent upon how the LED control bits are programmed. When the LEDSEL bit in the LEDCTRL register is set high, the COM and SEG lines will be setup as CMOS output drivers to drive the LED display. The COM and SEG lines can be set to be either active high or active low using bits in the LEDCTRL register. This provides 4 different timing modes. These are COM low active, SEG low active; COM low active, SEG high active; COM high active, SEG low active; COM high active, SEG high active. The COM and SEGlines will have a reverse polarity when in the non-active state when the display is off. For the LED driver there are a total of 5 different duty cycle selections which are Static, 1/4, 1/8, 1/12 and 1/16. The The frame rate of each duty cycle will be between 55Hz and 75Hz. LCD Voltage Source and Biasing The time and amplitude varying signals generated by the LCD Driver function require the generation of several voltage levels for their operation. The number of voltage levels used by the signal depends upon the value of the BIAS bit in the LCDCTRL register. The device can have either R type or C type biasing selected via a configuration option. Selecting the C type biasing will enable an internal charge pump whose multiplier ratio can be selected using an additional configuration option. For R type biasing an external LCD voltage source must be supplied on pin VLCD1 to generate the internal biasing voltages. This could be the microcontroller power supply or some other voltage source. For the R type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The voltage VA is equal to the externally supplied voltage source applied to pin VLCD1. VB is generated internally by the microcontroller and will have a value equal to VLCD1/2. For the R type 1/3 bias selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA is equal to VLCD1, VB is equal to VLCD12/3 while VC is equal to VLCD11/3. In addition to selecting 1/2 or 1/3 bias, several values of bias resistor can be chosen using bits in the LCDCTRL register. Different values of internal bias resistors can be selected using the RSEL0 and RESEL1 bits in the LCDCTRL register. This along with the voltage on pin VLCD1 will determine the bias current. The connection to the VMAX pin depends upon the voltage that is applied to VLCD1. If the VDD voltage is greater than the voltage applied to the VLCD1 pin then the VMAX pin should be connected to VDD, otherwise the VMAX pin should be connected to pin VLCD1. Note that no external capacitors or resistors are required to be connected if R type biasing is used. Condition VDD > VLCD1 Otherwise VMAX Connection Connect VMAX to VDD Connect VMAX to VLCD1
R Type Bias Current VMAX Connection For C type biasing an external LCD voltage source must also be supplied on pin VLCD1 to generate the internal biasing voltages. The C type biasing scheme uses an internal charge pump circuit, which in the case of the 1/3 bias selection can generate voltages higher than what is supplied on VLCD1. This feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the LCD. An additional charge pump capacitor must also be connected between pins C1 and C2 to generate the necessary voltage levels. For the C type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The voltage VA is generated internally and has a value of VLCD1. VB will have a value equal to VA0.5. For the C type 1/2 bias configuration VC is not used. For the C type 1/3 bias selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA is generated internally and has a value of VLCD11.5. VB will have a value equal to VA 2/3 and VC will have a value equal to VA 1/3. The connection to the VMAX pin depends upon the bias and the voltage that is applied to VLCD1, the details are shown in the table. Note that C type biasing is not available on the 52-pin QFP package device types. On these package types, pins C1, C2 and VLCD2 are not provided. It is recommended that a 0.1mF capacitor is connected between the V1 pin and ground on the 52-pin QFP package types. It is extremely important to ensure that these charge pump generated internal voltages do not exceed the maximum VDD voltage of 5.5V. Note that the C-type bias type is not available on the 52-pin QFP package type. Biasing Type 1/3 Bias 1/2 Bias VMAX Connection
VDD>VLCD11.5 Connect VMAX to VDD Otherwise VDD>VLCD1 Otherwise Connect VMAX to V1 Connect VMAX to VDD Connect VMAX to VLCD1
C Type Biasing VMAX Connection
Rev. 1.10
33
September 14, 2009
HT56R67/HT56R668/HT56R678
COM0 VDD VSS VDD VSS VDD VSS
Programming Considerations Certain precautions must be taken when programming the LCD/LED. One of these is to ensure that the Display Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the Display Memory are in an unknown condition after power-on. As the contents of the Display Memory y will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. One additional consideration that must be taken into account is what happens when the microcontroller enters a Power Down condition. The LCDEN control bit in the LCDCTRL or LEDEN bit in the LEDCTRL register permits the display to be powered off to reduce power consumption. If this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the LCD. After Power-on, note that as the LCDEN and LEDEN bits will be cleared to zero, the display function will be disabled. The accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. The huge range of various permutations only permit a few types to be displayed here.
COM1
SEG
LED 1/4 Duty, COM High Active, SEG Low Active, Display Off
0
1 2
3
71
C O M 0 in lo w a c tiv e S E G in lo w a c tiv e
VDD VSS VDD VSS
C O M 0 in lo w a c tiv e S E G in h ig h a c tiv e
VDD VSS VDD VSS
C O M 0 in h ig h a c tiv e S E G in lo w a c tiv e
VDD VSS VDD VSS
C O M 0 in h ig h a c tiv e S E G in h ig h a c tiv e
VDD VSS VDD VSS
SEG0 COM0
SEG1
SEG2
SEGn
LED Static Mode Normal Operation
COM1
COM2
COMn
LCD Panel Equivalent Circuit
Rev. 1.10
34
September 14, 2009
HT56R67/HT56R668/HT56R678
0 1 2 3 0 1 2 3 VDD COM0 VSS VDD COM1 VSS VDD COM2 VSS VDD COM3 VSS VDD SEG0 VSS VDD SEG1 VSS
LED 1/4 Duty, COM High Active, SEG Low Active, Normal Operation
D u r in g R e s e t o r in H A L T M o d e CO M 0,CO M 1 A ll s e g m e n t o u tp u ts N o r m a l O p e r a tio n M o d e COM0 COM1 A ll s e g m e n ts O F F C O M 0 s e g m e n ts O N C O M 1 s e g m e n ts O N A ll s e g m e n ts O N
1 F ra m e
VA VB VSS VA VB VSS
VA VB VSS VA VB VSS VA VB VSS VA VB VA VB VSS VA VB VSS VSS
Note: For 1/2 Bias, VA=VLCD1, VB=VLCD11/2 for both R and C type. LCD Driver Output - Type A - 1/2 Duty, 1/2 Bias
Rev. 1.10
35
September 14, 2009
HT56R67/HT56R668/HT56R678
D u r in g R e s e t o r in H A L T M o d e CO M 0,CO M 1,CO M 2 A ll s e g m e n t o u tp u ts N o r m a l O p e r a tio n M o d e COM0 COM1 COM2 A ll s e g m e n ts O F F C O M 0 s e g m e n ts O N C O M 1 s e g m e n ts O N C O M 2 s e g m e n ts O N C O M 0 , 1 s e g m e n ts O N C O M 0 , 2 s e g m e n ts O N C O M 1 , 2 s e g m e n ts O N A ll s e g m e n ts O N
1 F ra m e
VA VB VSS VA VB VSS VA VB VA VB VSS VA VB VSS VA VB VSS VA VB VSS VA VB VA VB VA VB VA VB VA VB VA VB VSS VSS VSS VSS VSS VSS VSS
Note: For 1/2 Bias, the VA=VLCD1, VB=VLCD11/2 for both R and C type. LCD Driver Output - Type A- 1/3 Duty, 1/2 Bias
Rev. 1.10
36
September 14, 2009
HT56R67/HT56R668/HT56R678
D u r in g R e s e t o r in H A L T M o d e CO M 0,CO M 1,CO M 2,CO M 3 VA VB VC VSS VA VB VC VSS VA VB VC VA VB VC VSS VA VB VC VSS VA VB VC VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VSS VSS COM1
A ll s e g m e n t o u tp u ts N o r m a l O p e r a tio n M o d e COM0
1 F ra m e
COM2 COM3
A ll s e g m e n ts O F F
C O M 0 s e g m e n ts O N
C O M 1 s e g m e n ts O N
C O M 2 s e g m e n ts O N
C O M 3 s e g m e n ts O N
C O M 0 , 1 s e g m e n ts O N
C O M 0 , 2 s e g m e n ts O N
C O M 0 , 3 s e g m e n ts O N ( o th e r c o m b in a tio n s a r e o m itte d ) A ll s e g m e n ts O N
Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD12/3 and VC=VLCD11/3. For 1/3 C type bias, the VA=VLCD11.5, VB=VLCD1 and VC=VLCD11/2. LCD Driver Output - Type A - 1/4 Duty, 1/3 Bias
Rev. 1.10
37
September 14, 2009
HT56R67/HT56R668/HT56R678
D u r in g R e s e t o r in H A L T M o d e CO M 0,CO M 1,CO M 2 VA VB VC VSS VA VB VC VSS VA VB VC VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VSS COM1
A ll s e g m e n t o u tp u ts N o r m a l O p e r a tio n M o d e COM0
1 F ra m e
COM2 A ll s e g m e n ts O F F
C O M 0 s e g m e n ts O N
C O M 1 s e g m e n ts O N
C O M 2 s e g m e n ts O N
C O M 0 , 1 s e g m e n ts O N
C O M 0 , 2 s e g m e n ts O N
C O M 1 , 2 s e g m e n ts O N
A ll s e g m e n ts O N
Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD12/3 and VC=VLCD11/3. For 1/3 C type bias, the VA=VLCD11.5, VB=VLCD1 and VC=VLCD11/2. LCD Driver Output - Type A - 1/3 Duty, 1/3 Bias
Rev. 1.10
38
September 14, 2009
HT56R67/HT56R668/HT56R678
VA COM0 VB VSS VA COM1 VB VSS VA VB On O ff On O ff On O ff On O ff On O ff On O ff On O ff VSS VA VB O ff On O ff On O ff On O ff On O ff On O ff On O ff On VSS VA VB O ff O ff O ff O ff O ff O ff O ff O ff O ff O ff O ff O ff O ff O ff VSS
COM0 S e g m e n ts O n
COM1 S e g m e n ts O n
COM0 S e g m e n ts O ff
Note: For 1/2 bias, the VA=VLCD1, VB=VLCD11/2 for both R and C type. LCD Driver Output - Type B - 1/2 Duty, 1/2 Bias
Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices contain several 8-bit and 16-bit count-up timers. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. The provision of a prescaler to the clock circuitry of the 8-bit Timer/Event Counter also gives added range to this timer. There are two types of registers related to the Timer/Event Counters. The first are the registers that contain the actual value of the Timer/Event Counter and into which an initial value can be preloaded. Reading from these registers retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and determines how the Timer/Event Counter is to be used. The Timer/Event Counters can have the their clock configured to come from an internal clock source. In addition, their clock source can also be configured to come from an external timer pin. Configuring the Timer/Event Counter Input Clock Source The internal timers clock can originate from various sources. The system clock source is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. For the 8-bit Timer/Event Counter this internal clock source is fSYS which is also divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register, TMRnC, bits TnPSC0~ TnPSC2. For the 16-bit Timer/Event Counter this internal clock source can be chosen from a combination of internal clocks using a configuration option and the TnS bit in the TMRnC register. An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin TMR0, TMR1, TMR2 or TMR3 depending upon which timer is used. Depending upon the condition of the TnE bit, each high to low, or low to high transition on the external timer pin will increment the counter by one.
Rev. 1.10
39
September 14, 2009
HT56R67/HT56R668/HT56R678
Device No. of 8-bit Timers Timer Name All Devices 3 Timer/Event Counter 0 Timer/Event Counter 2 Timer/Event Counter 3 TMR0 TMR2 TMR3 TMR0C TMR2C TMR3C 1 Timer/Event Counter 1 TMR1L/TMR1H TMR1C The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. At the same time the data in the low byte buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. It must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Registers TMR0C, TMR1C, TMR2C, TMR3C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. It is the Timer Control Register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer Control Register, which are known as the bit pair TnM1/TnM0, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as TnE. An additional TnS bit in the 16-bit Timer/Event Counter control register is used to determine the clock source for the Timer/Event Counter.
Timer Register Name
Control Register Name No. of 16-bit Timers Timer Name Timer Register Name Control Register Name
Timer Registers - TMR0, TMR1L/TMR1H, TMR2, TMR3 The timer registers are special function registers located in the Special Purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit Timer/Event Counters, these registers are known as TMR0, TMR2 or TMR3. For the 16-bit Timer/Event Counter, a pair of registers are required and are known as TMR1L/TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted when using instructions to preload data into the low byte timer register, the data will only be placed in a low byte buffer and not directly into the low byte timer register.
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D a ta B u s P r e lo a d R e g is te r TnPSC 2~TnPSC 0 (1 /1 ~ 1 /1 2 8 ) TnM 1 TnM 0 T im e r /E v e n t C o u n te r TnO N TnE 8 - b it T im e r /E v e n t C o u n te r 2 O v e r flo w to In te rru p t PFD0 R e lo a d
fS
TM Rn
YS
7 - s ta g e P r e s c a le r F ilte r
T im e r /E v e n t C o u n te r M o d e C o n tro l
F ilte r O n /O ff C o n fig u r a tio n o p tio n
8-bit Timer/Event Counter Structure
D a ta B u s L o w B y te B u ffe r 1 6 - B it P r e lo a d R e g is te r R e lo a d
E x te rn a l 3 2 7 6 8 H z
M U
In te rn a l 3 2 K -IN T
X
fS fS
YS UB
/4
M U
X
TnM 1
TnM 0
C o n fig u r a tio n O p tio n TM Rn
TnS F ilte r
T im e r /E v e n t C o u n te r M o d e C o n tro l TnO N TnE
H ig h B y te
Low
B y te 2
1 6 - b it T im e r /E v e n t C o u n te r
O v e r flo w to In te rru p t PFD1
F ilte r O n /O ff C o n fig u r a tio n o p tio n
16-bit Timer/Event Counter Structure
PFD0 PFD1
M U
X
PFD
C o n fig u r a tio n O p tio n
b7 TnM 1 TnM 0 b0 TnO N TnE TnPSC 2 TnPSC 1 TnPSC 0 TM RnC R e g is te r (n = 0 , 2 , 3 ) ct SC0 0 1 0 1 0 1 0 1
T im e r p r e s c a le r r a te s e le TnP TnPSC 2 TnPSC 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 E ventC 1:coun 0:coun P u ls e W 1 : s ta rt 0 : s ta rt o u n te r a c tiv e e d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g
T im e r 1 :1 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 6 2 4
R a te
28
e s e le c t t a c tiv e e d g e s e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin TnM 1 T 0 0 1 1 g m ode nM 0 no 0 ev 1 tim 0 pu 1 s e le c t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register - TMRnC Rev. 1.10 41 September 14, 2009
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b7 TnM 1 TnM 0 TnS TnO N TnE b0 TM RnC R e g is te r (n = 1 )
N o t im p le m e n te d , r e a d a s " 0 " Ev 1: 0: Pu 1: 0: entC coun coun ls e W s ta rt s ta rt oun ton ton id th coun coun te r a c tiv e e d g fa llin g e d g e r is in g e d g e M e a s u re m e n tin g o n r is in g tin g o n fa llin g e s e le c t t a c tiv e e d g e s e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le T im e r c lo c k s o u r c e 1 : fS U B (3 2 7 6 8 H z o r 3 2 K R C ) 0 : fS Y S /4 O p e r a tin g m o d e TnM 1 TnM 0 no 0 0 ev 0 1 1 tim 0 1 1 pu s e le c t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register - TMRnC
Configuring the Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode Bit7 Bit6 1 0
Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Bit7 Bit6 0 1
In this mode the internal clock, fSYS , is used as the internal clock for 8-bit Timer/Event Counter 0 and fSUB or fSYS/4 is used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON or TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. Each time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
P r e s c a le r O u tp u t
In this mode, the external timer pin, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TnE, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an I/O pin, to en-
In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart Rev. 1.10 42 September 14, 2009
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sure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Power Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. Configuring the Pulse Width Measurement Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode Bit7 Bit6 1 1 Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily Made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. The
In this mode the internal clock, fSYS, is used as the internal clock for the 8-bit Timer/Event Counter and fSUB or fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. If the Active Edge Select bit TnE, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, the
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
E x te rn a l T M R P in In p u t TnO N - w ith T n E = 0
P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3 +4
Pulse Width Measure Mode Timing Chart Rev. 1.10 43 September 14, 2009
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first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second is to ensure that the port control register configures the pin as an input. Programmable Frequency Divider - PFD The Programmable Frequency Divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O pin. The clock source for the PFD circuit can originate from either Timer/Event Counter 0 or Timer/Event Counter 1 overflow signal selected via configuration option. The output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. The timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The timer will then be automatically reloaded with the preload register value and continue counting-up. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set to 1. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to 0. Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. Prescaler Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of external pins for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register must be set high to ensure that the pin is setup as an input. Any pull-high resistor on these pins will remain valid even if the pin is used as a Timer/Event Counter input. Timer/Event Counter Pins Internal Filter The external Timer/Event Counter pins are connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the external Timer/Event Counter input signal. As this internal filter circuit will consume a limited amount of power, a configuration option is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. Care must be taken when using the filter on/off configuration option as it will be applied not only to both external Timer/Event Counter pins but also to the external interrupt input pins. Individual Timer/Event Counter or external interrupt pins cannot be selected to have a filter on/off function.
T im e r O v e r flo w PFD C lo c k
P A 3 D a ta
PFD
O u tp u t a t P A 3
PFD Output Control
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Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.
org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter 0 interrupt vector jmp tmrint ; jump here when the Timer/Event Counter 0 overflows : org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine tmrint: : ; Timer/Event Counter 0 main program placed here : reti : : begin: ;setup Timer 0 registers mov a,09bh ; setup Timer 0 preload value mov tmr0,a; mov a,081h ; setup Timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov int0c,a set tmr0c.4 ; start Timer/Event Counter 0 - note mode bits must be previously setup Rev. 1.10 45 September 14, 2009
HT56R67/HT56R668/HT56R678
Pulse Width Modulator
The devices contains a series of Pulse Width Modulation, PWM, outputs. Useful for such applications such as motor speed control, the PWM function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. Part No. Channels PWM Mode Output Register Pin Names PD0~ PD3 PWM0L~ PWM3L PWM0H~ PWM3H 8+4 PWM Mode Modulation Each full PWM cycle, as it is 12-bits wide, has 4096 clock periods. However, in the 8+4 PWM mode, each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as i in the table. Each one of these sixteen sub-cycles contains 256 clock cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit4~bit11 is denoted here as the DC value. The second group which consists of bit0~bit3 is known as the AC value. In the 8+4 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. Parameter Modulation cycle i (i=0~15) AC (0~15) iAll devices
4
8+4
PWM Overview A register pair, located in the Data Memory is assigned to each Pulse Width Modulator output and are known as the PWM registers. It is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. The PWM registers also contain the enable/disable control bit for the PWM outputs. To increase the PWM modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. The PWM clock source is the system clock fSYS. This method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 12-bits wide, the overall PWM cycle frequency is fSYS/4096. However, when in the 8+4 mode of operation, the PWM modulation frequency will be fSYS/256. PWM Modulation Frequency fSYS/256 PWM Cycle Frequency fSYS/4096 PWM Cycle Duty (PWM register value)/4096
8+4 Mode Modulation Cycle Values The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 16 individual modulation cycles, numbered 0~15 and how the AC value is related to the PWM value. PWM Output Control The four PWM0~PWM3 outputs are shared with pins PD0~PD3. To operate as a PWM output and not as an I/O pin, bit 0 of the relevant PWM register bit must be set high. A zero must also be written to the corresponding bit in the PDC port control register, to ensure that the PWM0 output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM 12-bit value has been written into the PWM register pair register, writing a 1 to the corresponding PD data register will enable the PWM data to appear on the pin. Writing a 0 to the bit will disable the PWM output function and force the output low. In this way, the Port D data output register bits, can also be used as an on/off control for the PWM function. Note that if the enable bit in the PWM register is set high to enable the PWM function, but a 1 has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections.
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PWM Programming Example The following sample program shows how the PWM output is setup and controlled. mov mov clr clr set set : : clr a,64h pwm0h,a pwm0l pdc.0 pwm0en pd.0 : : pd.0 ; ; ; ; ; ; setup PWM0 value to 1600 decimal which is 640H setup PWM0H register value setup PWM0L register value setup pin PD0 as an output set the PWM0 enable bit Enable the PWM0 output
; PWM0 output disabled - PD0 will remain low
fS
YS
/2
[P W M ] = 1 6 0 0 PW M [P W M ] = 1 6 0 1 PW M [P W M ] = 1 6 0 2 PW M 1 0 1 /2 5 6 1 0 1 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 1 /2 5 6 1 0 1 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 1 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6
[P W M ] = 1 6 1 5 PW M PW M 1 0 1 /2 5 6 m o d u la tio n p e r io d : 2 5 6 /fS M o d u la tio n c y c le 0
YS
1 0 1 /2 5 6 M o d u la tio n c y c le 1 PW M
1 0 1 /2 5 6 M o d u la tio n c y c le 2 c y c le : 4 0 9 6 /fS
YS
1 0 1 /2 5 6 M o d u la tio n c y c le 1 5
1 0 1 /2 5 6 M o d u la tio n c y c le 0
8+4 PWM Mode
PW M 0H~PW M 3H H ig h B y te R e g is te r s b7 11 b0 4 5 b7 3 2
PW M 0L~PW M 3L L o w B y te R e g is te r s b0 PW M nEN 0
10
9
8
7
6
1
PW M
R e g is te r s (n = 0 ~ 3 )
P W M O n /O ff C o n tro l 1 : P W M e n a b le 0 : I/O p in e n a b le N o t im p le m e n te d , r e a d a s " 0 " P W M A C V a lu e b its 0 ~ 3 P W M D C V a lu e b its 4 ~ 1 1
PWM Register Pairs
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Part No. All devices Input Channels 8 Conversion Bits 12 Input Pins PB0~PB7 Bit 7 D3 Bit 6 D2 Bit 5 D1 Bit 4 D0 D8 Bit 3 3/4 D7 Bit 2 3/4 D6 Bit 1 3/4 D5 Bit 0 3/4 D4
Register ADRL ADRH
D11 D10 D9
A/D Data Registers A/D Converter Control Registers - ADCR, ACSR To control the function and operation of the A/D converter, two control registers known as ADCR and ACSR are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 bits in the ADCR register define the channel number. As the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port B are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the 3-bit address on PCR2~PCR0 has a value of 111, then all eight pins, namely AN0~AN7 will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. The START bit in the register is used to start and reset
YS
The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers - ADRL, ADRH The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. Only the high byte register, ADRH, utilises its full 8-bit contents. The low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. In the following table, D0~D11 is the A/D conversion data result bits.
fS
ACSR
R e g is te r
A D O N B B it A /D E n a b le P B 0 /A N 0 P B 1 /A N 1 P B 7 /A N 7
C lo c k D iv id e r N A /D R e fe r e n c e V o lta g e AV DD A /D P o s itiv e P o w e r S u p p ly ADRL ADRH A /D AV
SS
ADC
A /D D a ta R e g is te r s
G ro u n d
PC R0~PC R2
AD CS0~ADCS2
START
EOCB
ADCR R e g is te r
A/D Converter Structure Rev. 1.10 48 September 14, 2009
HT56R67/HT56R668/HT56R678
b7 START EO CB PCR2 PCR1 PCR0 ACS2 ACS1 b0 ACS0 ADCR R e g is te r channel CS1 ACS0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1
S e le c t A /D A ACS2 0 0 0 0 1 1 1 1 P o rt B A /D P PCR2 0 0 0 0 1 1 1 1
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 u r a tio n s o rt B0 B0 B0 B0 B0 B0 B0 BA ena ~PB ~PB ~PB ~PB ~PB ~PB /D b 1 2 3 4 5 7 chann le d a s A e n a b le e n a b le e n a b le e n a b le e n a b le e n a b le e ls N0 da da da da da da - a ll o ff sAN sAN sAN sAN sAN sAN 0~A 0~A 0~A 0~A 0~A 0~A N1 N2 N3 N4 N5 N7
c h a n n e l c o n fig CR1 PCR0 P 0 0 P 1 0 P 0 1 P 1 1 P 0 0 P 1 0 P 0 1 1 1 P
E n d o f A /D c o n v e r s io n fla g 1 : A /D c o n v e r s io n w a itin g o r in p r o g r e s s 0 : A /D c o n v e r s io n e n d e d S ta r t th e A /D c o n v e r s io n 0 (R) 1 (R) 0 : S ta rt 0 (R) 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
A/D Converter Control Register - ADCR
the A/D converter. When themicrocontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a 1 and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the ACSR register. Controlling the on/off function of the A/D converter circuitry is implemented using the ADONB bit in the ACSR
register and the value of the PCR bits in the ADCR register. Both the ADONB bit must cleared to 0 and the value of the PCR bits must have a non-zero value for the A/D converter to be enabled. PCR 0 >0 >0 ADONB x 0 1 A/D Off On Off
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2, ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of 4MHz. For system clock speeds in excess of 4MHz, the ADCS2, ADCS1 and ADCS0 bits should not be set to 000. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period.
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A/D Clock Period (tAD) fSYS ADCS2, ADCS1, ADCS0=000 (fSYS/2) 2ms 1ms 500ns 250ns* 167ns* ADCS2, ADCS1, ADCS0=001 (fSYS/8) 8ms 4ms 2ms 1ms 667ns A/D Clock Period Examples
b7 TEST
ADONB
ADCS2, ADCS1, ADCS0=010 (fSYS/32) 32ms 16ms 8ms 4ms 2.67ms
ADCS2, ADCS1, ADCS0=011 Undefined Undefined Undefined Undefined Undefined
1MHz 2MHz 4MHz 8MHz 12MHz
b0 ADCS2ADCS1ADCS0
ACSR
R e g is te r e y s te y s te y s te nde y s te y s te y s te nde m m fin m m m fin m c lo c lo c lo ed c lo c lo c lo ed c k /2 c k /8 c k /3 2 c k /4 c k /1 6 ck
S e le c t A /D c o n v e r te r c lo c k s o u r c ADCS0 ADCS2 ADCS1 :s 0 0 0 :s 1 0 0 :s 0 0 1 :u 1 0 1 :s 0 1 0 :s 1 1 0 :s 0 1 1 :u 1 1 1 N o t im p le m e n te d , r e a d a s " 0 " A /D O n /O ff c o n tr o l b it 1 : d is a b le 0 : e n a b le F o r te s t m o d e u s e o n ly
A/D Converter Control Register - ACSR A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port B. Bits PCR2~PCR0 in the ADCR register, determine whether the input pins are setup as normal Port B input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PBC port control register to enable the A/D input as when the PCR2~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own power supply pins AVDD and AVSS and a VREF reference pin. The analog input values must not be allowed to exceed the value of VREF. Initialising the A/D Converter The internal A/D converter must be initialised in a special way. Each time the Port B A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialise the A/D converter after Rev. 1.10 50 the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process.
* Step 1
Select the required A/D conversion clock by correctly programming bits ADCS2, ADCS1 and ADCS0 in the register.
* Step 2
Enable the A/D by clearing the in the ACSR register to zero.
* Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the register.
* Step 4
Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2 into a single ADCR register programming operation. September 14, 2009
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PC R2~ PCR0 000B 100B 101B 000B
ADONB tO ADC m o d u le ON on
N2ST
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e
o ff
on
o ff
START
EOCB
AC S2~ ACS0
xxxB P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e p o r t c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te :
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
xxxB
tA D C c o n v e r s io n tim e
A /D
YS
tA D C c o n v e r s io n tim e
A /D c lo c k m u s t b e fs y s , fS Y S /2 , fS Y S /4 , fS Y S /8 , fS Y S /1 6 o r fS tA D C S = 4 tA D tA D C = tA D C S + n * tA D ; n = b it c o u n t o f A D C r e s o lu tio n
/3 2
A/D Conversion Timing
* Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0 interrupt control register must be set to 1, the multi-function interrupt enable bit, EMFI, in the INTC1 register and the A/D converter interrupt bit, EADI, in the INTC1 register must also be set to 1.
* Step 6
internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. Programming Considerations When programming, special attention must be given to the A/D channel selection bits in the register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens the power supplied to the internal A/D circuitry will be reduced resulting in a reduction of supply current. This ability to reduce power by turning off the internal A/D function by clearing the A/D channel selection bits may be an important consideration in battery powered applications. The ADONB bit in the ACSR register can also be used to power down the A/D function. Another important programming consideration is that when the A/D channel selection bits change value, the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not required to be re-initialised. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. 51 September 14, 2009
The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from 0 to 1 and then to 0 again. Note that this bit should have been originally set to 0.
* Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. The setting up and operation of the A/D converter function is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller
Rev. 1.10
HT56R67/HT56R668/HT56R678
Example: using an EOCB polling method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bit mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the ; following START ; signal (0-1-0) must be issued ; instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Example: using the interrupt method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bit mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs ; and select AN0 to be connected to the A/D ; As the Port B channel bits have changed the ; following START signal(0-1-0) must be issued ; : Start_conversion: clr START set START clr START clr ADF set EADI set EMFI set EMI : : : ; ADC interrupt service routine ADC_: mov acc_stack,a a,STATUS mov status_stack,a : : mov a,ADRL mov adrl_buffer,a mov a,ADRH mov adrh_buffer,a : : EXIT__ISR: mov a,status_stack mov STATUS,a mov a,acc_stack clr ADF reti
; ; ; ; ; ;
reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable multi-function interrupt enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory ; ; ; ; read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register
; restore STATUS from user defined memory ; restore ACC from user defined memory ; clear ADC interrupt flag
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1 .5 L S B FFFH FFEH FFDH A /D C o n v e r s io n R e s u lt 03H 02H 01H 0 1 2 3 4093 4094 4095 4096 ( VDD ) 4096 0 .5 L S B
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function A/D Transfer Function As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD/4096. The diagram show the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level. The communication is full duplex and operates as a slave/master type, where the MCU can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, here, as only a single select pin, SCS, is provided only one slave device can be connected to the SPI bus.
S P I M a s te r SCK SDO SDI SCS S P I S la v e SCK SDI SDO SCS
SPI Master/Slave Connection
* SPI Interface Operation
Serial Interface Function
The device contains a Serial Interface Function, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using a bit in an internal register. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. Rev. 1.10 53
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMCTL0/SIMCTL2 register. After the SPI configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMCTL0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilised. The SPI function in this device offers the following features:

Full duplex synchronous data transfer Both Master and Slave modes LSB first or MSB first data transmission modes Transmission complete flag
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Rising or falling active clock edge WCOL and CSEN bit enabled or disable select
Configuration Option SIM Function SPI CSEN bit SPI WCOL bit
Function SIM interface or I/O pins Enable/Disable Enable/Disable
The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN, SIMEN and SCS. In the table I, Z represents an input floating condition. There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMCTL0 register will have no effect. Another two SIM configuration options determine if the CSEN and WCOL bits are to be used.
SPI Interface Configuration Options SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMDR data register and two control registers SIMCTL0 and SIMCTL2. Note that the SIMCTL1 register is only used by the I2C interface.
Pin
Master/Salve SIMEN=0 Z Z Z Z
Master - SIMEN=1 CSEN=0 Z O I, Z H: CKPOL=0 L: CKPOL=1 CSEN=1 L O I, Z H: CKPOL=0 L: CKPOL=1 CSEN=0 Z O I, Z I, Z
Slave - SIMEN=1 CSEN=1 SCS=0 I, Z O I, Z I, Z CSEN=1 SCS=1 I, Z Z Z Z
SCS SDO SDI SCK Note:
Z floating, H output high, L output low, I Input, Ooutput level, I,Z input floating (no pull-high) SPI Interface Pin Status
D a ta B u s S IM D R S D I P in SDO E n a b le /D is a b le B usy S ta tu s C o n fig u r a tio n O p tio n W C O L F la g T R F F la g P in
T x /R x S h ift R e g is te r
C K E G b it C K P O L b it S C K P in fS Y S fS U B T im e r /E v e n t C o u n te r S C S P in CSEN b it
C lo c k E d g e /P o la r ity C o n tro l
C lo c k S o u r c e S e le c t
C o n fig u r a tio n O p tio n E n a b le /D is a b le
SPI Block Diagram
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b7 S IM 2 b0 S IM 1 S IM 0 PCKEN P C K P S C 1 P C K P S C 0 S IM E N S IM C T L 0 R e g is te r N o t im p le m e n t e d , r e a d a s '0 " S P I/I2C O n /O f c o n tro l 1 : e n a b le 0 : d is a b le P e r ip h e r a l C lo c k C o n tr o l - d e s c r ib e d e ls e w h e r e S P I/I2C S IM 2 0 0 0 0 1 1 1 1 M a s te r /S la S IM 1 S 0 0 1 1 0 0 1 1 v e a n d C lo c k IM 0 m a s te r, 0 m a s te r, 1 0 m a s te r, 1 m a s te r, 0 m a s te r, 1 S la v e I2C m o d 0 N otuse 1 C o n tro l fS fS fS fS e d
YS YS YS UB
/4
/1 6 /6 4
T im e r /E v e n t C o u n te r 0 o u tp u t/2
SPI/I2C Control Register - SIMCTL0
b7 HCF
b0 HAAS HBB HTX TXAK SRW RXAK S IM C T L 1 R e g is te r R e c e iv e a c k n o w le d g e fla g 1 : n o t a c k n o w le d g e d 0 : a c k n o w le d g e d N o t im p le m e n te d , r e a d a s " 0 " M a s te r d a ta r e a d /w r ite r e q u e s t fla g 1 : re q u e s t d a ta re a d 0 : r e q u e s t d a ta w r ite T r a n s m it a c k n o w le d g e fla g 1 : d o n 't a c k n o w le d g e 0 : a c k n o w le d g e T r a n s m it/R e c e iv e m o d e 1 : tr a n s m it m o d e 0 : r e c e iv e m o d e I2 C b u s b u s y fla g 1:busy 0:notbusy C a llin g a d d r e s s m a tc h e d fla g 1 : m a tc h e d 0 : n o t m a tc h e d D a ta tr a n s fe r fla g 1 : tr a n s fe r c o m p le te 0 : tr a n s fe r n o t c o m p le te
I2C Control Register - SIMCTL1
b7 CKPOL CKEG M LS CSEN W COL
b0 TRF S IM C T L 2 R e g is te r T r a n s m it/R e c e iv e c o m p le te fla g 1 : fin is h e d 0 : in p r o g r e s s W r ite c o llis io n fla g 1 : c o llis io n 0 : n o c o llis io n S C S p in e n a b le 1 : e n a b le 0 : S C S flo a tin g D a ta s h ift o r d e r 1:M SB 0:LSB S P I C lo c k E d g e S e le c t 1 : s e e te x t 0 : s e e te x t S P I C lo c k P o la r ity 1 : s e e te x t 0 : s e e te x t N o t im p le m e n te d , r e a d a s " 0 "
SPI Control Register - SIMCTL2
Rev. 1.10
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The SIMDR register is used to store the data being transmitted and received. The same register is used by b o t h t h e S P I and I 2 C f u n c t i o n s . B ef o r e t h e microcontroller writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMDR register. After the data is received from the SPI bus, the microcontroller can read it from the SIMDRregister. Any transmission or reception of data from the SPI bus must be made via the SIMDR register. Bit 7 6 5 4 3 2 1 0 1 1 1 1 There are also two control registers for the SPI interface, SIMCTL0 and SIMCTL2. Note that the SIMCTL2 register also has the name SIMAR which is used by the I2C function. The SIMCTL1 register is not used by the SPI function, only by the I 2 C function. Register SIMCTL0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMCTL0 register is also used to control the Peripheral Clock prescaler. Register SIMCTL2 is used for other control functions such as LSB/MSB selection, write collision flag etc. The following gives further explanation of each SIMCTL1 register bit:
* SIMIDLE
the SPI Slave Mode is selected then the clock will be supplied by an external Master device. SIM0 0 0 0 0 SIM1 0 0 1 1 0 0 1 1 SIM2 0 1 0 1 0 1 0 0 SPI Master/Slave Clock Control and I2C Enable SPI Master, fSYS/4 SPI Master, fSYS/16 SPI Master, fSYS/64 SPI Master, fSUB SPI Master Timer/Event Counter 0 output/2 SPI Slave I2C mode Not used
Label SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 R/W POR R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X
SPI Control Register - SIMCTL2 The SIMCTL2 register is also used by the I2C interface but has the name SIMAR.
* TRF
The TRF bit is the Transmit/Receive Complete flag and is set high automatically when an SPI data transmission is completed, but must be cleared by the application program. It can be used to generate an interrupt.
* WCOL
The SIMIDLE bit is used to select if the SPI interface continues running when the device is in the IDLE mode. Setting the bit high allows the SPI interface to maintain operation when the device is in the Idle mode. Clearing the bit to zero disables any SPI operations when in the Idle mode. This SPI/I2C idle mode control bit is located at CLKMOD register bit4.
* SIMEN
The WCOL bit is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMDR register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option.
* CSEN
The bit is the overall on/off control for the SPI interface. When the SIMEN bit is cleared to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will be in a floating condition and the SPI operating current will be reduced to a minimum value. When the bit is high the SPI interface is enabled. The SIMconfiguration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program.
* SIM0~SIM2
The CSEN bit is used as an on/off control for the SCS pin. If this bit is low then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option.
* MLS
This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
* CKEG and CKPOL
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the Timer/Event Counter. If Rev. 1.10 56
These two bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOL bit determines the base condition of the clock line, if the bit is high then the SCK line will be low when the clock is inactive. When the CKPOL bit is low then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOL. September 14, 2009
HT56R67/HT56R668/HT56R678
S IM E N = 1 , C S E N = 0 ( E x te r n a l P u ll- H ig h ) SCS S C K (C K P O L = 1 , C K E G = 0 ) S C K (C K P O L = 0 , C K E G = 0 ) S C K (C K P O L = 1 , C K E G = 1 ) S C K (C K P O L = 0 , C K E G = 1 ) SDO SDO (C K E G = 0 ) (C K E G = 1 )
D 7 /D 0 D 7 /D 0 D 6 /D 1 D 6 /D 1 D 5 /D 2 D 5 /D 2 D 4 /D 3 D 4 /D 3 D 3 /D 4 D 3 /D 4 D 2 /D 5 D 2 /D 5 D 1 /D 6 D 1 /D 6 D 0 /D 7 D 0 /D 7
S IM E N , C S E N = 1
S D I D a ta C a p tu re W r ite to S IM D R
SPI Master Mode Timing
SCS
S C K (C K P O L = 1 ) S C K (C K P O L = 0 ) SDO S D I D a ta C a p tu re W r ite to S IM D R ( S D O n o t c h a n g e u n til fir s t S C K e d g e )
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
SPI Slave Mode Timing (CKEG=0)
SCS S C K (C K P O L = 1 ) S C K (C K P O L = 0 ) SDO S D I D a ta C a p tu re W r ite to S IM D R ( S D O c h a n g e a s s o o n a s w r itin g o c c u r ; S D O = flo a tin g if S C S = 1 ) N o te : F o r S P I s la v e m o d e , if S IM E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d a n d ig n o r e th e S C S le v e l.
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
SPI Slave Mode Timing (CKEG=1)
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September 14, 2009
HT56R67/HT56R668/HT56R678
A S P I tra n s fe r C le a r W C O L
W r ite D a ta in to S IM D R
M a s te r
m a s te r o r s la v e
S la v e Y W CO L=1?
S IM [2 :0 ]= 0 0 0 , 0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0
S IM [2 :0 ]= 1 0 1
N
N c o n fig u r e C SEN and M LS
T r a n s m is s io n c o m p le te d ? (T R F = 1 ? ) Y
S IM E N = 1
R e a d D a ta fro m S IM D R
A
C le a r T R F
T ra n s fe r F in is h e d ?
N
Y END
SPI Transfer Control Flowchart
Rev. 1.10
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HT56R67/HT56R668/HT56R678
CKPOL 0 0 1 1 CKEG 0 1 0 1 SCK Clock Signal High Base Level Active Rising Edge High Base Level Active Falling Edge Low Base Level Active Falling Edge Low Base Level Active Rising Edge
S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r
SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMDR register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMDR register will be transmitted and any data on the SDI pin will be shifted into the SIMDR register. The master should output an SCS signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled before/after an SCS signal is received. The SPI will continue to function even after a HALT instruction has been executed. I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications.
* I2C Interface Operation
There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMCTL0 register will have no effect. A configuration option exists to allow a clock other than the system clock to drive the I2C interface. Another configuration option determines the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. SIM SIM function I2C clock I2C debounce Function SIM interface or SEG pins I2C runs without internal clock Disable/Enable No debounce, 1 system clock; 2 system clocks
I2C Interface Configuration Options
* I2C Registers
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode.
There are three control registers associated with the I2C bus, SIMCTL0, SIMCTL1 and SIMAR and one data register, SIMDR. The SIMDR register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMDR register. After the data is received from the I2C bus, the microcontroller can read it from the SIMDR register. Any transmission or reception of data from the I2C bus must be made via the SIMDR register. Note that the SIMAR register also has the name SIMCTL2 which is used by the SPI function. Bits SIMIDLE , SIMEN and bits SIM0~SIM2 in register SIMCTL0 are used by the I2C interface. The SIMCTL0 register is shown in the above SPI section.
Rev. 1.10
59
September 14, 2009
HT56R67/HT56R668/HT56R678
D a ta B u s I2C D a ta R e g is te r (S IM D R ) S la v e A d d r e s s R e g is te r (S IM A R ) A d d re s s C o m p a ra to r A d d re s s M a tc h H A A S B it
H T X B it
S C L P in S D A P in M U X
D ir e c tio n C o n tr o l
S h ift R e g is te r
I2C
In te rru p t
D a ta in L S B D a ta O u t M S B
R e a d /w r ite S la v e
SRW
B it
E n a b le /D is a b le A c k n o w le d g e T r a n s m it/R e c e iv e C o n tr o l U n it 8 - b it D a ta C o m p le te D e te c t S ta rt o r S to p H C F B it H B B B it
I2C Block Diagram
SIMIDLE The SIMIDLE bit is used to select if the I2C interface continues running when the device is in the IDLE mode. Setting the bit high allows the I2C interface to maintain operation when the device is in the Idle mode. Clearing the bit to zero disables any I2C operations when in the Idle mode. This SPI/I2C idle mode control bit is located at CLKMOD register bit4. SIMEN The SIMEN bit is the overall on/off control for the I2C interface. When the SIMEN bit is cleared to zero to disable the I2C interface, the SDA and SCL lines will be in a floating condition and the I2C operating current will be reduced to a minimum value. In this condition the pins can be used as SEG functions. When the bit is high the I2C interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMENbit changes from low to high the contents of the I2C control registers will be in an unknown condition and should therefore be first initialised by the application program SIM0~SIM2 These bits setup the overall operating mode of the SIM function. To select the I2C function, bits SIM2~ SIM0 should be set to the value 110. RXAK The RXAK flag is the receive acknowledge flag. When the RXAK bit has been reset to zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When in the transmit mode, the transmitter checks the RXAK bit to determine if the receiver wishes to receive the next byte. The transmitter will therefore continue sending out data until the RXAK bit is set high. When this occurs, the transmitter will release the SDA line to allow the master to send a STOP signal to release the bus.
SRW The SRW bit is the Slave Read/Write bit. This bit determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address match, that is when the HAAS bit is set high, the device will check the SRW bit to determine whether it should be in transmit mode or receive mode. If the SRW bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. When the SRW bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. TXAK The TXAK flag is the transmit acknowledge flag. After the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be reset to zero before further data is received. HTX The HTX flag is the transmit/receive mode bit. This flag should be set high to set the transmit mode and low for the receive mode. HBB The HBB flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will occur when a START signal is detected. The flag will be reset to zero when the bus is free which will occur when a STOP signal is detected. HASS The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. HCF The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.

Rev. 1.10
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HT56R67/HT56R668/HT56R678
I2C Control Register - SIMAR The SIMARregister is also used by the SPI interface but has the name SIMCTL2. The SIMARregister is the location where the 7-bit slave address of the microcontroller is stored. Bits 1~7 of the SIMAR register define the microcontroller slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMARregister, the microcontroller slave device will be selected. Note that the SIMAR register is the same register as SIMCTL2 which is used by the SPI interface. I2C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the microcontroller matches that of the transmitted address, the HAAS bit in the SIMCTL1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the microcontroller slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: Step 1 Write the slave address of the microcontroller to the I2C bus address register SIMAR. Step 2 Set the SIMEN bit in the SIMCTL0 register to 1 to enable the I2C bus. Step 3 Set the ESIM bit of the interrupt control register to enable the I2C bus interrupt.
2
S ta rt
W r ite S la v e A d d re s s to S IM A R
S E T S IM [2 :0 ]= 1 1 0 S E T S IM E N
D is a b le CLR EH I P o ll H IF to d e c id e w h e n to g o to I2C B u s IS R
I2C B u s In te rru p t= ?
E n a b le
SET EHI W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
I2C Bus Initialisation Flow Chart
* Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by the microcontroller, which is only a slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.
* Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMCTL1 register. The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMDR register, or in the receive mode where it must implement a dummy read from the SIMDR register to release the SCL line.
b0
b7 SA6
SA5
SA4
SA3
SA2
SA1
SA0
S IM A R
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 " I2C
2
d e v ic e s la v e a d d r e s s
I C Slave Address Register - SIMAR Rev. 1.10 61 September 14, 2009
HT56R67/HT56R668/HT56R678
SCL S ta rt S la v e A d d r e s s SRW ACK
SDA
1
0
1 1
0
1
0
1
0
SCL
D a ta
ACK
S to p
1 SDA S=S SA= SR= M =S D=D A=A P=S S ta rt (1 S la v e SRW la v e d a ta (8 C K (R to p (1 SA
0
0
1
0
1
0
0
b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) SR M D A D
2
A S
SA
SR
M
D
A D
A
P
I C Communication Timing Diagram
S ta rt
No
HAAS=1 ? Yes Yes
Yes No
No
HTX=1 ?
SRW =1 ?
R e a d fro m S IM D R
SET HTX
C LR H TX C LR TXAK
RETI Yes RXAK=1 ? No C LR H TX C LR TXAK W r ite to S IM D R
W r ite to S IM D R
D um m y R ead F ro m S IM D R
RETI
RETI
D um m y R ead fro m S IM D R
RETI
RETI
I2C Bus ISR Flow Chart
Rev. 1.10
62
September 14, 2009
HT56R67/HT56R668/HT56R678
* SRW Bit * Receive Acknowledge Bit
The SRW bit in the SIMCTL1 register defines whether the microcontroller slave device wishes to read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW bit is set to 1 then this indicates that the master wishes to re a d da t a f r o m t he I 2 C bus , t her e f o r e t h e microcontroller slave device must be setup to send data to the I2C bus as a transmitter. If the SRW bit is 0 then this indicates that the master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup to read data from the I2C bus as a receiver.
* Acknowledge Bit
When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is setup as a transmitter will check the RXAK bit in the SIMCTL1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.
Peripheral Clock Output
The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCLK, is shared with one of the LCD segment lines, the required pin function is chosen via PCKEN in SIMCTL0 register. The Peripheral Clock function is controlled using the SIMCTL0 register. The clock source for the Peripheral Clock Output can originate from either the Timer/Event Counter 0 divided by two or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMCTL0 register is the overall on/off control, setting the bit high enables the Peripheral Clock, clearing it disables it. The required division ratio of the system clock is selected using the PCKPSC0 and PCKPSC1 bits in the same register. If the system enters the Sleep Mode this will disable the Peripheral Clock output.
PCKPSC0 PCKPSC1 PCKEN
After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. This acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS bit is high, the addresses have matched and the microcontroller slave device must check the SRW bit to determine if it is to be a transmitter or a receiver. If the SRW bit is high, the microcontroller slave device should be setup to be a transmitter so the HTX bit in the SIMCTL1 register should be set to 1 if the SRW bit is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMCTL1 register should be set to 0.
* Data Byte
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the SDA line and the master will send out a STOP signal to release control of the I2C bus. The corresponding data will be stored in the SIMDR register. If setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the SIMDR register. If setup as a receiver, the microcontroller slave device must read the transmitted data from the SIMDR register.
SCL SDA
fS
YS
1,4,8
T im e r /E v e n t C o u n te r 0 2 S le e p M o d e
PC LK orSEG S e le c t
PC LK or SEG
Peripheral Clock Block Diagram
S ta r t b it
D a ta s ta b le
D a ta a llo w change
S to p b it
Data Timing Diagram
Rev. 1.10
63
September 14, 2009
HT56R67/HT56R668/HT56R678
b7 S IM 2 b0 S IM 1 S IM 0 PCKEN P C K P S C 1 P C K P S C 0 S IM E N S IM C T L 0 R e g is te r N o t im p le m e n t e d , r e a d a s '0 " S P I/I2C O n /O f c o n tro l 1 : e n a b le 0 : d is a b le P C K c lo c k s e le c t PCKPSC1 PCKPSC0 0 0 0 1 1 0 1 1 P e r ip h e r a l c lo c k e n a b le 1 : c lo c k a n d o u tp u t e n a b le 0 : c lo c k a n d o u tp u t d is a b le S P I M a s te r /S la v e a n d c lo c k c o n tr o l - d e s c r ib e d e ls e w h o s e C lo c k S o u r c e
YS
fS
fS Y S /4 fS Y S /8 T im e r /E v n e t C o u n te r 0 2
Peripheral Clock Output Control - SIMCTL0
Buzzer
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complementary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to select from one of three buzzer options. The first option is for both pins PA0 and PA1 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. The buzzer is driven by the internal clock source, , which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer frequency, can originate from three different sources, the 32768Hz oscillator, the 32K_INT oscillator or the System oscillator/4, the choice of which is determined by the fS clock source configuration option. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. There are no internal registers associated with the buzzer frequency. If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register has no control over the BZ buzzer pin PA1.
fS
YS
/4
32768H z 3 2 K _ IN T
fS S o u rc e C o n fig u r a tio n O p tio n
fS
C o n fig u r a tio n O p tio n D iv id e b y 2 2 ~ 2 9
BZ BZ
Buzzer Function
Rev. 1.10
64
September 14, 2009
HT56R67/HT56R668/HT56R678
PA0/PA1 Pin Function Control PAC Register PAC0 0 0 0 0 1 1
x stands for dont care D stands for Data 0 or 1
PAC Register PAC1 0 0 1 1 0 1
PA Data Register PA0 1 0 1 0 x x
PA Data Register PA1 x x x x D x
Output Function PA0=BZ PA1=BZ PA0=0 PA1=0 PA0=BZ PA1=input line PA0=0 PA1=input line PA0=input line PA1=D PA0=input line PA0=input line
If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then the PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer output, if set low pin PA0 will remain low. In this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0. If the PAC0 bit of the PAC port control register is set high, then pin PA0 can still be used as an input even though the configuration option has configured it as a BZ buzzer output.
Note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always behave as an input pin. This arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit.
In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control Note: The above drawing shows the situation where both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as output. The data setup on pin PA1 has no effect on the buzzer outputs.
Rev. 1.10
65
September 14, 2009
HT56R67/HT56R668/HT56R678
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are controlled by the action of the external INT0, INT1 and PINT pins, while the internal interrupts are controlled by the Timer/Event Counter overflows, the Time Base interrupt, the RTC interrupt, the SPI/I2C interrupt and the the A/D converter interrupt. Interrupt Registers Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the INTC0, INTC1, and MFIC/MFIC0/MFIC1 registers, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A Timer/Event Counter overflow, Time Base, RTC overflow, SPI/I2C data transfer complete, an end of A/D conversion or the external interrupt line being triggered will all generate an interrupt request by setting their corresponding request flag. When this happens and if their appropriate interrupt enable bit is set, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be Rev. 1.10 66 The A/D converter interrupt, Real Time clock interrupt, Time Base interrupt and External Peripheral interrupt all share the same interrupt vector which is 18H. Each of these interrupts have their own own individual interrupt flag but also share the same MFF interrupt flag. The MFF flag will be cleared by hardware once the Multi-function interrupt is serviced, however the individual interrupts that have triggered the Multi-function interrupt need to be cleared by the application program. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bits, EEI0 and EEI1, must first be set. Additionally the correct interrupt edge type must be selected using the INTEDGE register to enable the external interrupt function and to choose the trigger edge type. An actual external interrupt will take place when the external interrupt request flag, EIF0 or EIF1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PD4 and PD5 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 register has been set. The pin must also be setup as an input by setting the corresponding PDC.4 and PDC.5 bits in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external September 14, 2009 immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. Interrupt Source External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow SPI/I2C Interrupt Multi-function Interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
HT56R67/HT56R668/HT56R678
b7 T0F E IF 1 E IF 0 E T 0 I E E I1 E E I0 b0 EMI IN T C 0 R e g is te M a s te r in te r r u p t g lo b a l e n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l in te r r u p t 0 e n a b le 1 : e n a b le 0 : d is a b le E x te r n a l in te r r u p t 1 e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le E x te r n a l in te r r u p t 0 r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e E x te r n a l in te r r u p t 1 r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register - INTC0
b7 M FF S IM F T1F E M F I E S IM
b0 ET1I IN T C 1 R e g is te r T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le S P I/I2 C in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le M u lti- fu n c tio n in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e S P I/I2 C in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e M u lti- fu n c tio n in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register - INTC1
Rev. 1.10
67
September 14, 2009
HT56R67/HT56R668/HT56R678
b7 PEF TBF RTF ADF EPI b0 ETBI ERTI EADI M F IC /M F IC 0 R e g is te r A /D c o n v e r te r in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le R e a l T im e C lo c k in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e B a s e in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le E x te r n a l p e r ip h e r a l in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le A /D c o n v e r te r in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e R e a l T im e C lo c k in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e B a s e in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e E x te r n a l p e r ip h e r a l in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e
Interrupt Control Register - MFIC/MFIC0
b7 T3F T2F ET3I
b0 ET2I M F IC 1 R e g is te r T im e r /E v e n t C o u n te r 2 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 3 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 2 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 3 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register - MFIC1
Rev. 1.10
68
September 14, 2009
HT56R67/HT56R668/HT56R678
A u to m a tic a lly C le a r e d b y IS R except fo r A D F , T B F , R T F a n d T 2 F M a n u a lly S e t o r C le a r e d b y S o ftw a r e A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity E x te rn a l In te rru p t R e q u e s t F la g E IF 0 E x te rn a l In te rru p t R e q u e s t F la g E IF 1 T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g T 1 F S P I/I2C In te r r u p t R e q u e s t F la g S IM F M u lti- fu n c tio n In te r r u p t R e q u e s t F la g M F F E E I0 EMI H ig h
E E I1
ET0I In te rru p t P o llin g
ET1I
E S IM
EM FI
Low
A /D C o n v e rte r In te r r u p t R e q u e s t F la g A D F R e a l T im e C lo c k In te r r u p t R e q u e s t F la g R T F T im e B a s e In te r r u p t R e q u e s t F la g T B F E x te r n a l P e r ip h e r a l In te r r u p t R e q u e s t F la g P E F T im e r /E v e n t C o u n te r 2 In te r r u p t R e q u e s t F la g T 2 F T im e r /E v e n t C o u n te r 3 In te r r u p t R e q u e s t F la g T 3 F
EADI
ERTI
ETBI
EPI
ET2I
ET3I
Interrupt Structure
interrupt vector at location 04H or 08H, will take place. When the interrupt is serviced, the external interrupt request flags, EIF0 or EIF1, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. The INTEDGE register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising and falling edge types can be chosen along with an option to allow both edge types to trigger an external interrupt. Note that the INTEDGE register can also be used to disable the external interrupt function.
F ilte r O n /O ff C o n fig u r a tio n O p tio n IN T C 0 IN T C 1 F ilte r F ilte r MCU
The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. As this internal filter circuit will consume a limited amount of power, a configuration option is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. Care must be taken when using the filter on/off configuration option as it will be applied not only to both the external interrupt pins but also to the Timer/Event Counter external input pins. Individual external interrupt or Timer/Event Counter pins cannot be selected to have a filter on/off function.
E x te rn a l IN T .0 E x te rn a l IN T .1
Rev. 1.10
69
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HT56R67/HT56R668/HT56R678
b7 b0 IN T 1 S 1 IN T 1 S 0 IN T 0 S 1 IN T 0 S 0 IN T E D G E R e g is te r IN T 0 E d g e S e IN T 0 S 1 IN 0 0 1 1 le c t T0S0 0 1 0 1
d is a b le r is in g e d g e tr ig g e r fa llin g e d g e tr ig g e r d u a l e d g e tr ig g e r
IN T 1 E d g e S e le c t IN T 1 S 1 IN T 1 S 0 0 0 1 0 0 1 1 1
d is a b le r is in g e d g e tr ig g e r fa llin g e d g e tr ig g e r d u a l e d g e tr ig g e r
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Active Edge Register - INTEDGE External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function interrupt. For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, EPI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual external peripheral interrupt will take place when the external interrupt request flag, PEF, is set, a situation that will occur when a negative transition, appears on the PINT pin. The external peripheral interrupt pin is pin-shared with one of the segment pins, and is configured as a peripheral interrupt pin via a configuration option. When the interrupt is enabled, the stack is not full and a negative transition type appears on the external peripheral interrupt pin, a subroutine call to the Multi-function interrupt vector at location18H, will take place. When the external peripheral interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the PEF flag will not be automatically reset, it has to be cleared by the application program. Timer/Event Counter Interrupt For a Timer/Event Counter 0 or Timer/Event Counter 1 interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ET0I or ET1I must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, T0F or T1F is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 0CH or 10C, will take place. When the interrupt is serviced, the timer interrupt request flag, T0F or T1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Timer Event Counter 0 and Timer/Event Counter 1 have their own individual interrupt vectors, however the interrupt vector for Timer/Event Counter 2 or Timer/Event counter 3 is contained within the Multi-function Interrupt. For a Timer/Event Counter 2 or a Timer/Event counter 3 interrupt to occur, the global interrupt enable bit, EMI, Timer/Event Counter 2 or Timer/Event counter 3 interrupt enable bit, ET2I or ET3I, and Multi-function interrupt enable bit, EMFI, must first be set. An actual interrupt will take place when the Timer/Event Counter 2 or Timer/Event counter 3 request flag, T2F or T3F, is set, a situation that will occur when the Timer/Event Counter 2 or Timer/Event counter 3 overflows. When the interrupt is enabled, the stack is not full and the Timer/Event Counter 2 or Timer/Event counter 3 overflows, a subroutine call to the Multi-function interrupt vector at location 18H, will take place. When the Timer/Event 2 or Timer/Event counter 3 interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the T2F or T3F flag will not be automatically reset, it has to be cleared by the application program. A/D Interrupt The A/D Interrupt is contained within the Multi-function Interrupt. For an A/D Interrupt to be generated, the global interrupt enable bit, EMI, A/D Interrupt enable bit, EADI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual A/D Interrupt will take place when the A/D Interrupt request flag, ADF, is set, a situation that will occur when the A/D conversion process has finished. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the Multi-function interrupt vector at location18H, will take place. When the A/D Interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the ADF flag will not be automatically reset, it has to be cleared by the application program.
Rev. 1.10
70
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HT56R67/HT56R668/HT56R678
SPI/I2C Interface Interrupt For an SPI/I C interrupt to occur, the global interrupt enable bit, EMI, and the corresponding interrupt enable bit, ESIM must be first set. An actual SPI/I2C interrupt will take place when the SPl/I2C request flag, SIMF, is set, a situation that will occur when a byte of data has been transmitted or received by the SPI/I2C interface or when an I2C address match occurs. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPI/I2C interface or an I2C address match occurs, a subroutine call to the SPI/I2C interrupt vector at location 14H, will take place. When the interrupt is serviced, the SPI/I2C request flag, SIMF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Multi-function Interrupt An additional interrupt known as the Multi-function interrupt is provided. Unlike the other interrupts, this interrupt has no independent source, but rather is formed from four or five other existing interrupt sources, namely the A/D Converter interrupt, Time Base interrupt, Real Time Clock interrupt, External Peripheral interrupt and the Timer 2 overflow interrupt. For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the Multi-function interrupt enable bit, EMFI, must first be set. An actual Multi-function interrupt will take place when the Multi-function interrupt request flag, MFF, is set. This will occur when either a Time Base overflow, a Real Time Clock overflow, an A/D conversion completion, an External Peripheral Interrupt or Timer 2 overflow interrupt is generated. When the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the Multi-function interrupt occurs, a subroutine call to the Multi-function interrupt vector at location 018H will take place. When the interrupt is serviced, the Multi-Function request flag, MFF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that the request flags from the original source of the Multi-function interrupt, namely the Time-Base interrupt, Real Time Clock interrupt, A/D Converter interrupt, External Peripheral interrupt or Timer 2 overflow interrupt will not be automatically reset and must be manually reset by the application program.
2
Real Time Clock Interrupt The Real Time Clock Interrupt is contained within the Multi-function Interrupt. For a Real Time Clock interrupt to be generated, the global interrupt enable bit, EMI , Real Time Clock interrupt enable bit, ERTI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual Real Time Clock interrupt will take place when the Real Time Clock request flag, RTF, is set, a situation that will occur when the Real Time Clock overflows. When the interrupt is enabled, the stack is not full and the Real Time Clock overflows, a subroutine call to the Multi-function interrupt vector at location18H, will take place. When the Real Time Clock interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the RTF flag will not be automatically reset, it has to be cleared by the application program. Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide an interrupt signal at fixed time periods. The RTC interrupt clock source originates from the internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is selected by programming the appropriate bits in the RTCC register to obtain longer RTC interrupt periods whose value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn controls the RTC interrupt period, can originate from three different sources, the 32768Hz oscillator, 32K_INT oscillator or the System oscillator/4, the choice of which is determine by the fS clock source configuration option. Note that the RTC interrupt period is controlled by both configuration options and an internal register RTCC. A configuration option selects the source clock for the internal clock fS, and the RTCC register bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio can be programmed from 28 to 215.
fS
YS
/4
32768H z 3 2 K _ IN T
fS S o u rc e C o n fig u r a tio n O p tio n
fS
D iv id e b y 2 8 ~ 2 Setby RTCC R e g is te r
15
R T C In te rru p t 2 12/fS ~ 2 15/fS
RT2
RT1
RT0
RTC Interrupt
Rev. 1.10
71
September 14, 2009
HT56R67/HT56R668/HT56R678
b7 LVDO QOSC LVDC RT2 RT1 b0 RT0
RTCC R e g is te r
RTC RT2 0 0 0 0 1 1 1 1
In te r r u p t P e r io d RT0 RT1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1
Pe 28 29 21 21 21 21 21 21
r io d /fS /fS 0 /fS 1 /fS 2 /fS 3 /fS 4 /fS 5 /fS
L o w V o lta g e D e te c to r C o n tr o l 1 : e n a b le 0 : d is a b le R T C O s c illa to r Q u ic k - s ta r t 1 : d is a b le 0 : e n a b le L o w V o lta g e D e te c to r O u tp u t 1 : lo w v o lta g e d e te c te d 0 : n o r m a l v o lta g e N o t im p le m e n te d , r e a d a s " 0 "
Real Time Clock Control Register - RTCC Time Base Interrupt The Time Base Interrupt is contained within the Multi-function Interrupt. For a Time Base Interrupt to be generated, the global interrupt enable bit, EMI,Time Base Interrupt enable bit, ETBI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual Time Base Interrupt will take place when the Time Base Interrupt request flag, TBF, is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to the Multi-function interrupt vector at location18H, will take place. When the Time Base Interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the TBF flag will not be automatically reset, it has to be cleared by the application program. The purpose of the Time Base function is to provide an interrupt signal at fixed time periods. The Time Base interrupt clock source originates from the Time Base interrupt clock source originates from the internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is selected by configuration options to provide longer Time Base interrupt periods. The Time Base interrupt time-out period ranges from 212/fS~215/fS. The clock source that generates fS, which in turn controls the Time Base interrupt period, can originate from three different sources, the 32768Hz oscillator, the 32K_INT internal oscillator or the System oscillator/4, the choice of which is determine by the fS clock source configuration option. Essentially operating as a programmable timer, when the Time Base overflows it will set a Time Base interrupt flag which will in turn generate an Interrupt request via the Multi-function Interrupt vector. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1 and MFIC registers until the corresponding interrupt is serviced or until the request flag is cleared by the application program. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the status or other registers are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
fS
YS
/4
32768H z 3 2 K _ IN T
fS S o u rc e C o n fig u r a tio n O p tio n
fS
C o n fig u r a tio n O p tio n D iv id e b y 2 1 2 ~ 2 1 5
T im e B a s e In te r r u p t 2 12/fS ~ 2 15/fS
Time Base Interrupt Rev. 1.10 72 September 14, 2009
HT56R67/HT56R668/HT56R678
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold.
0 .1 ~ 1 m F
inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t C h ip R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
V 0 .0 1 m F * * 1N4148*
DD
VDD 10kW ~ 100kW R E S /P A 7
300W *
Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
VSS
Note:
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be
* It is recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant External RES Circuit
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t C h ip R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
RES Reset Timing Chart 73 September 14, 2009
Rev. 1.10
HT56R67/HT56R668/HT56R678
* Low Voltage Reset - LVR
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options. The VLVR value will be selected as a pair in conjunction with a Low Voltage Detect value.
LVR tR S S T T im e - o u t C h ip R e s e t
STD
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
S S T T im e - o u t
STD
Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared I/O ports will be setup as inputs Stack Pointer will point to the top of the stack
C h ip R e s e t
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
Input/Output Ports Stack Pointer
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
Rev. 1.10
74
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The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register MP0 MP1 BP ACC PCL TBLP TBLH RTCC STATUS INTC0 TMR0 TMR0C TMR1H TMR1L TMR1C TMR2 TMR2C TMR3 TMR3C PA PAC PB PBC PC PCC PD PDC PWM0L PWM0H PWM1L PWM1H INTC1 PWM2L PWM2H PWM3L Reset (Power-on) xxxx xxxx xxxx xxxx -00- 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0111 --00 xxxx 0000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 ---0 0000 0000 0000 ---0 0000 0000 -000 --00 0000 ---0 0000 0000 0000 ---0 RES Reset (Normal Operation) uuuu uuuu uuuu uuuu -00- 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0111 --uu uuuu 0000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 ---0 0000 0000 0000 ---0 0000 0000 -000 --00 0000 ---0 0000 0000 0000 ---0 WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu -00- 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0111 --1u uuuu 0000 0000 xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 ---0 0000 0000 0000 ---0 0000 0000 -000 --00 0000 ---0 0000 0000 0000 ---0 WDT Time-out (HALT) uuuu uuuu uuuu uuuu -uu- uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu ---u uuuu uuuu -uuu --uu uuuu ---u uuuu uuuu uuuu ---u
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Register PWM3H ADRL ADRH ADCR ACSR CLKMOD PAWU PAPU PBPU PCPU PDPU INTEDGE LCDCTRL LCDOUT1 LCDOUT2 LEDCTRL MISC MFIC/MFIC0 MFIC1 SIMCTL0 SIMCTL1 SIMDR SIMAR/SIMCTL2 Note: Reset (Power-on) 0000 0000 xxxx ---xxxx xxxx 0100 0000 10--000 RES Reset (Normal Operation) 0000 0000 xxxx ---xxxx xxxx 0100 0000 10--000 WDT Time-out (Normal Operation) 0000 0000 xxxx ---xxxx xxxx 0100 0000 10--000 WDT Time-out (HALT) uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu uu--uuu
0000 0x11 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0000 0000 -000 0000 0000 1010 0000 0000 --00 --00 1110 0000 1000 00-1 xxxx xxxx 0000 0000
0000 0x11 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0000 0000 -000 0000 0000 1010 0000 0000 --00 --00 1110 0000 1000 00-1 xxxx xxxx 0000 0000
0000 0x11 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0000 0000 -000 0000 0000 1010 0000 0000 --00 --00 1110 0000 1000 00-1 xxxx xxxx 0000 0000
uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- --uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu --uu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu
u stands for unchanged x stands for unknown - stands for unimplemented
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Three types of system clocks can be selected while various clock source options are provided for maximum flexibility. All oscillator options are selected through the configuration options. System Clock Configurations There are three methods of generating the system clock, two high oscillators and an externally supplied clock. The two high oscillators are the external crystal/ceramic oscillator and the external RC network. Selecting whether the low frequency or high oscillator is used as the system oscillator is implemented using the HLCLK bit in the CLKMOD register. The source clock for the high oscillator is chosen via configuration option. The frequency of the slow clock is also determined using the SLOWC0~SLOWC2 bits in the CLKMOD register. System Crystal/Ceramic Oscillator After selecting the external crystal configuration option, the simple connection of a crystal across OSC1 and OSC2, is normally all that is required to create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification. In most applications, resistor RP1 is not required, however for those applications where the LVR function is not used, RP1 may be necessary to ensure the oscillator stops running when VDD falls below its operating range. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. An additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1MHz, or low, which is defined as below 1 MHz. More information regarding oscillator applications is located on the Holtek website.
C1
Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz 455kHz (see Note 2) Note: C1 3/4 3/4 3/4 3/4 10pF C2 3/4 3/4 3/4 3/4 10pF
1. C1 and C2 values are for guidance only. 2. XTAL mode configuration option: 455kHz. 3. RP1= 5MW~10MW is recommended.
Crystal Recommended Capacitor Values External System RC Oscillator After selecting the correct configuration option, using the external system RC oscillator requires that a resistor, with a value between 47kW and 1.5MW, is connected between OSC1 and VDD, and a 470pF capacitor is connected to ground. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor ROSC refer to the Appendix section for typical RC Oscillator vs. Temperature and VDD characteristics graphics. Note that an internal capacitor together with the external resistor, ROSC, are the components which determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation. This external capacitor should be added to improve oscillator stability if the open-drain OSC2 output is utilised in the application circuit. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins.
V
DD
R
OSC
OSC1 470pF
OSC1
R C2
P1
fS
YS
/4 N M O S O p e n D r a in
OSC2
RC Oscillator
OSC2
Internal 32K_INT Oscillator When microcontrollers enter a power down condition, their internal clocks are normally switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep some internal functions operational, 77 September 14, 2009
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such as timers, even when the microcontroller is in the Power-down mode. To do this, the device has a 32K_INT oscillator, which is a fully integrated free running RC oscillator with a typical period of 31.2ms at 5V, requiring no external components. It is selected via configuration option. When the device enters the Power Down Mode, the system clock will stop running, however the 32K_INT oscillator will continue to run if selected to keep various internal functions operational. will always function normally, only there is more power consumption associated with the quick start-up function. 32768Hz Oscillator C1 and C2 Values Crystal Frequency 32768Hz Note: C3 8pF C4 10pF
1. C3 and C4 values are for guidance only. 2. RP2=5M~10MW is recommended.
32768 Hz Crystal Recommended Capacitor Values
In te rn a l 3 2 K _ IN T
External Oscillator
fR
C 32K
Internal 32K_INT Oscillator External 32768Hz Oscillator With a function similar to the internal 32K-INT 32KHz oscillator, that is to keep some device functions operational during power down, this device also has an external 32768Hz oscillator. This oscillator also remains active at all times, even when the microcontroller is in the Power-down mode. This clock source has a fixed frequency of 32768Hz and requires a 32768Hz crystal to be connected between pins OSC3 and OSC4. The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. A configuration option selects whether the external 32768Hz oscillator or the internal 32K_INT oscillator is selected. During power-up there is a time delay associated with the 32768Hz oscillator waiting for it to start-up. To minimise this time delay, bit 4 of the RTCC register, known as the QOSC bit, is provided to have a quick start-up function. During a power-up condition, this bit will be cleared to zero which will initiate the 32768Hz oscillator quick start-up function. However, as there is additional power consumption associated with this quick start-up function, to reduce power consumption after start-up takes place, it is recommended that the application program should set the QOSC bit high for about 2 seconds after power-on. It should be noted that, no matter what condition the QOSC bit is set to, the 32768Hz oscillator
C3 R C4
P2
The system clock can also be supplied by an externally supplied clock giving users a method of synchronising their external hardware to the microcontroller operation. This is selected using a configuration option and supplying the clock on pin OSC1. Pin OSC2 should be left floating if the external oscillator is used. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin, however as the filter circuit consumes a certain amount of power, a oscillator configuration option exists to turn this filter off. Not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source.
System Operating Modes
The devices have the ability to operate in several different modes. This range of operating modes, known as Normal Mode, Slow Mode, Idle Mode and Sleep Mode, allow the devices to run using a wide range of different slow and fast clock sources. The devices also possess the ability to dynamically switch between different clocks and operating modes. With this choice of operating functions users are provided with the flexibility to ensure they obtain optimal performance from the device according to their application specific requirements. Clock Sources In discussing the system clocks for the devices, they can be seen as having a dual clock mode. These dual clocks are what are known as a High Oscillator and the other as a divided frequency from high oscillator. The High Oscillator and Low frequency are the system clock sources and can be selected dynamically using the HLCLK bit in the CLKMOD register. The High Oscillator has the internal name fM whose source is selected using a configuration option from a choice of either an external crystal/resonator, external RC oscillator or external clock source. The Low frequency clock source, is further modified by the SLOWC0~SLOWC2 bits in the CLKMOD register to provide the low frequency clock source fSLOW.
32768H z
OSC3 32768H z OSC4
External 32768Hz Oscillator
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b7 S L O W C 2 S L O W C 1 S L O W C 0 S IM ID L E LTO HTO ID L E N b0 HLCLK CLKM OD fS Y S s e le c t 1 : fM 0 : fS L O W Id le m o d e 1 : e n a b le 0 : d is a b le H ig h o s c illa to r r e a d y fla g 1 : tim e - o u t 0 : n o n - tim e - o u t L o w o s c illa to r r e a d y fla g 1 : tim e - o u t 0 : n o n - tim e - o u t S P I/I2 C c o n tin u e s r u n n in g in Id le m o d e 1 :e n a b le 0 :d is a b le fS L O W s e le c tio n SLO W W C2 SLO W W C1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 SLO W W C0 0 1 0 1 0 1 0 1 fS fM fM fM fM fM fM
LO W
R e g is te r
/6 4 /3 2 /1 6 /8 /4 /2
Clock Control Register - CLKMOD
An additional sub internal clock, with the internal name fSUB, is a 32kHz clock source which can be sourced from either the internal 32K_INT oscillator or an external 32768 Hz crystal, selected by configuration option. Together with fSYS/4, it is used as a clock source for certain internal functions such as the LCD driver, Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The LCD clock source is the fSUB clock source divided by 8, giving a frequency of 4kHz. The internal clock fS, is simply a choice of either fSUB or fSYS/4, using a configuration option. Operating Modes After the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the CLKMOD register and use of the HALT instruction determine in which mode the device will be run. The devices can operate in the following Modes.
* Normal mode
fM on, fSLOW on, fSYS=fM, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT on/off depending upon the WDT configuration option and WDT control register.
* Slow mode
fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT on/off depending upon the WDT configuration option and WDT control register. Its important to note that fSLOW 100kHz for proper MCU operation.
* Idle mode
fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS/4, fLCD on/off depending upon the LCDEN bit, fWDT on/off depending upon the WDT configuration option and WDT control register.
* Sleep mode
fM, fSLOW, fSYS, fS, fLCD off, CPU off; fSUB, fWDT on/off depending upon the WDT configuration option and WDT control register.
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Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
quired if the configuration options have enabled the Watchdog Timer internal oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended.
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be reRev. 1.10 80
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N o rm a l M o d e
-u p ke wa
LT HA &
0 "= EN DL "I
fM O n , 3 2 7 6 8 H z o r 3 2 K _ IN T O n , fS Y S = fM
HA LT &
"ID
wa ke -u p
LE N" = 1
R e s e t "H L C L K "
S e t "H L C L K "
S le e p M o d e
Id le M o d e
fM O ff, 3 2 7 6 8 H z o r 3 2 K _ IN T O n * , fS Y S = O ff
fM O ff, 3 2 7 6 8 H z o r 3 2 K _ IN T O n #, fS Y S = O ff
HA LT &
wa ke -u p
"ID
S lo w
M ode
-u p ke wa
LT HA &
LE N" = 0
=1 N" LE "ID
fS
YS
fM O n , = fM /2 ~ fM /6 4
" * " D e p e n d s th e W D T e n a b le /d is a b le c o n d itio n .
" # " E ith e r th e 3 2 7 6 8 H z o r 3 2 K _ IN T m u s t b e O N .
Dual Clock Mode Operation
H ig h O s c illa to r OSC1 OSC1 OSC2 OSC1 OSC2 E x te rn a l C lo c k E x te rn a l RC E x te rn a l XTAL
E x te r n a l C lo c k F ilte r O ff C o n fig u r a tio n O p tio n E x te r n a l/X T A L /R C C o n fig u r a tio n O p tio n F ilte r MUX fM fM S lo w C lo c k C o n tro l SLO W C2 SLO W C1 SLO W C0 fM /2 , ... fM /6 4 H L C L K B it fS
MUX
YS
fS
LO W
OSC3 OSC4
E x te rn a l 32768H z C ry s ta l In te rn a l 3 2 K _ IN T Low O s c illa to r
32768H z
fS fS
YS UB
/4
MUX T 1 S B it
T im e r /E v e n t C o u n te r 1
3 2 K _ IN T
MUX fS U B C o n fig u r a tio n O p tio n
fS
UB
MUX fS C o n fig u r a tio n O p tio n fS
UB
fS
R T C in te r r u p t, T im e B a s e in te r r u p t, B u z z e r, W D T
fS
YS
/4
8
fL = fS
CD UB
/8
LCD 4kH z
Dual Clock Mode Structure Rev. 1.10 81
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Low Voltage Detector - LVD
The Low Voltage Detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. LVD Operation The LVD function must be first enabled via a configuration option after which bits 3 and 5 of the RTCC register are used to control the overall function of the LVD. Bit 3 is the enable/disable control bit and is known as LVDC, when set low the overall function of the LVD will be disabled. Bit 5 is the LVD detector output bit and is known as LVDO. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then the LVDO bit will change to a high value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By polling the LVDO bit in the RTCC register, the application program can therefore determine the presence of a low voltage condition. After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC register to zero. Note that if the LVD is enabled there will be some power consumption associated with its internal circuitry, however, by clearing the LVDC bit to zero the power can be minimised. It is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be affected with no influence on other microcontroller functions.
C L R W D T 1 F la g C L R W D T 2 F la g 1 o r 2 In s tr u c tio n s
There are a range of voltage values, selected using a configuration option, which can be chosen to activate the LVD.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the Watchdog Timer counter overflows. Watchdog Timer Operation The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer configuration option has been disabled, then any instruction relating to its operation will result in no operation. Most of the Watchdog Timer options, such as enable/disable, Watchdog Timer clock source and clear instruction type are selected using configuration options. In addition to a configuration option to enable the Watchdog Timer, there are four bits, WDTEN3~ WDTEN0, in the MISC register to offer an additional enable control of the Watchdog Timer. These bits must be set to a specific value of 1010 to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog Timer enabled. After power on these bits will have the disabled value of 1010.
C o n tro l L o g ic
fS
YS
/4
W D T O s c illa to r R T C O s c illa to r
W D T S o u rc e C o n fig u r a tio n O p tio n
CLR fS 8 - b it D iv id e r fS /2
8
7 - b it P r e s c a le r
2
W D T T im e - o u t (2 13/fS , 2 14/fS , 2 15/fS o r 2
16
/fS )
C o n fig O p tio n fS /2
12
, fS /2
13
, fS /2
14
o r fS /2
15
Watchdog Timer
b7 ODE3 b0 W DTEN0
ODE2
ODE1
ODE0
W DTEN3
W DTEN2
W DTEN1
M IS C
R e g is te r
W a tc h d o g T im e r E n a b le C o n tr o l W DTEN3 W DTEN2 W DTEN1 W DTEN0 1 1 0 0 a ll o th e r v a lu e s P A 0 ~ P A 3 O p e n D r a in C o n tr o l - d e s c r ib e d e ls e w h e r e
d is a b le e n a b le
Watchdog Timer Software Control - MISC
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One of the WDT clock sources is the internal fSUB, which can be sourced from either the 32K_INT internal oscillator or the 32768Hz oscillator. The 32K_INT internal oscillator has an approximate period of 31.2ms at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The 32768Hz oscillator is supplied by an external 32768Hz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. Whether the Watchdog Timer clock source is its own internal 32K_INT, the 32768Hz oscillator or fSYS/4, it is divided by 213~216, using configuration option to obtain the required Watchdog Timer time-out period. The max time out period is when the 216 option is selected. This time-out period may vary with temperature, VDD and process variations. As the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer counter before the clear instruction is executed. If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the Watchdog Timer will lose its protecting purposes. For systems that operate in noisy environments, using the 32K_INT RC oscillator is strongly recommended. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. Clearing the Watchdog Timer There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the Watchdog Timer. Note that for this second option, if CLR WDT1 is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. All options must be defined for proper system function, the details of which are shown in the table. No. Oscillator Options High Oscillator type selection - fM 1. External Crystal Oscillator 2. External RC Oscillator 3. Externally supplied clock - internal filter on 4. Externally supplied clock - internal filter off fSUB clock selection: 2 1. 32768Hz External Oscillator 2. 32K_INT Internal Oscillator 3 4 5 fS clock selection: fSUB or fSYS/4 XTAL mode selection: 455KHz or 1M~12MHz 32768Hz Crystal: enable or disable Options
1
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No. PFD Options 6 7 PA3: normal I/O or PFD output PFD clock selection: Timer/Event Counter 0 or Timer/Event Counter 1 Options
Buzzer Options 8 9 PA0/PA1: normal I/O or BZ/BZ or PA0=BZ and PA1 as normal I/O Buzzer frequency: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28, fS/29
Time Base Option 10 Time base time-out period: 212/fS, 213/fS, 214/fS, 215/fS,
LCD Option 11 LCD type: R or C - HT56R67 only
Watchdog Options 12 13 14 Watchdog Timer function: enable or disable CLRWDT instructions: 1 or 2 instructions WDT time-out period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS
LVD/LVR Options 15 16 17 LVD function: enable or disable LVR function: enable or disable LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V
SPI Options 18 19 20 I C Option 21 I2C debounce Time: no debounce, 1 system clock debounce, 2 system clock debounce
2
SIM pin enable/disable SPI_WCOL: enable/disable SPI_CSEN: enable/disable, used to enable/disable (1/0) software CSEN function
PINTB Option 22 External peripheral interrupt or Segment function
Timer/Event Counter and External Interrupt Pins Filter Option 24 Interrupt and Timer/Event Counter input pins internal filter On/Off control - applies to all pins
Lock Options 25 26 Lock All Partial Lock
Rev. 1.10
84
September 14, 2009
HT56R67/HT56R668/HT56R678
Application Circuits
Application Circuit for HT56R67
V 0 .0 1 m F
DD
VDD Reset C ir c u it R E S /P A 7
C O M /S E G
LCD Panel Z Z 2 D 2 3 7 R V
DD
0 .1 m F
1N4148
10kW ~ 100kW 300W
P PA PA P
0 .1 ~ 1 m F
P A 0 /B P A 1 /B PA A 3 /P F 4 /T M R 5 /T M R A6,PA ~
VSS
OSC
P B 0 /A N 0 P B 7 /A N 7 PC0~PC7 P D 0 /P W M 0 P D 3 /P W M 3 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 C1 0 .1 m F ~
R C S y s te m O s c illa to r 4 7 k W < R O S C < 1 .5 M W OSC1 fS
YS
470pF
/4
OSC2 OSC1 C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r d e ta ils r e g a r d in g C 1 , C 2 a n d R P1, c h e c k O s c illa to r s e c tio n 3 2 7 6 8 H z C ry s ta l O s c illa to r F o r d e ta ils r e g a r d in g C 3 ,C 4 a n d R P 2 , c h e c k O s c illa to r s e c tio n
C1 R
P1
OSC C ir c u it
OSC1 OSC2
C2 C3 R
P2
OSC2
OSC3
OSC C ir c u it
OSC3 OSC4
C2 V1
0 .1 m F VMAX VLC D 1 VLC D 2 0 .1 m F V
DD
C4
OSC4
OSC3 OSC4
O S C 3 , O S C 4 F lo a tin g
O S C C ir c u it
Rev. 1.10
85
September 14, 2009
HT56R67/HT56R668/HT56R678
Application Circuit for HT56R668/HT56R678
V 0 .0 1 m F
DD
VDD Reset C ir c u it R E S /P A 7
C O M /S E G
L C D /L E D Panel
0 .1 m F
1N4148
10kW ~ 100kW 300W
0 .1 ~ 1 m F
P PA PA P
VSS
P A 0 /B P A 1 /B PA A 3 /P F 4 /T M R 5 /T M R A6~PA D ~
Z Z 2 2 3 7 R V
DD
OSC
R C S y s te m O s c illa to r 4 7 k W < R O S C < 1 .5 M W OSC1 fS
YS
P B 0 /A N 0 P B 7 /A N 7 P D 0 /P W M 0 OSC C ir c u it OSC1 OSC2 P D 3 /P W M 3 P D 4 /IN T 0 P D 5 /IN T 1 P D 6 /T M R 0 P D 7 /T M R 1 OSC C ir c u it OSC3 OSC4 ~
470pF
/4
OSC2 OSC1 C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r d e ta ils r e g a r d in g C 1 , C 2 a n d R P1, c h e c k O s c illa to r s e c tio n 3 2 7 6 8 H z C ry s ta l O s c illa to r F o r d e ta ils r e g a r d in g C 3 ,C 4 a n d R P 2 , c h e c k O s c illa to r s e c tio n
C1 R
P1
C2 C3 R
P2
OSC2
OSC3
VLC D
V
DD
C4
OSC4
OSC3 OSC4
O S C 3 , O S C 4 F lo a tin g
O S C C ir c u it
Rev. 1.10
86
September 14, 2009
HT56R67/HT56R668/HT56R678
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller a p p l i c at i o n s . W i t h i n t h e H o l t e k microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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HT56R67/HT56R668/HT56R678
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z
Rev. 1.10
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HT56R67/HT56R668/HT56R678
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
89
September 14, 2009
HT56R67/HT56R668/HT56R678
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.10 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 90 September 14, 2009
HT56R67/HT56R668/HT56R678
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.10
91
September 14, 2009
HT56R67/HT56R668/HT56R678
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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HT56R67/HT56R668/HT56R678
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.10
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HT56R67/HT56R668/HT56R678
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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HT56R67/HT56R668/HT56R678
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.10
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HT56R67/HT56R668/HT56R678
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.10
97
September 14, 2009
HT56R67/HT56R668/HT56R678
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev. 1.10
98
September 14, 2009
HT56R67/HT56R668/HT56R678
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.10
99
September 14, 2009
HT56R67/HT56R668/HT56R678
Package Information
52-pin FP (14mm14mm) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K
Dimensions in mm Min. 17.30 13.90 17.30 13.90 3/4 3/4 2.50 3/4 3/4 0.73 0.10 0 Nom. 3/4 3/4 3/4 3/4 1.00 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 17.50 14.10 17.50 14.10 3/4 3/4 3.10 3.40 3/4 1.03 0.20 7
Rev. 1.10
100
September 14, 2009
HT56R67/HT56R668/HT56R678
64-pin L FP (7mm7mm) Outline Dimensions
C D 48 33 G H
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 0.13 1.35 3/4 0.05 0.45 0.09 0 Nom. 3/4 3/4 3/4 3/4 0.40 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 9.10 7.10 9.10 7.10 3/4 0.23 1.45 1.60 0.15 0.75 0.20 7
Rev. 1.10
101
September 14, 2009
HT56R67/HT56R668/HT56R678
100-pin FP (14mm20mm) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1.00 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.10
102
September 14, 2009
HT56R67/HT56R668/HT56R678
128-pin FP (14mm20mm) Outline Dimensions
C D 102 65 G I 103 64 H
F
A B
E
128
39
K 1 38 a J
Symbol A B C D E F G H I J K
Dimensions in mm Min. 17 13.9 23 19.9 3/4 3/4 2.5 3/4 3/4 0.65 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.5 0.2 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 23.5 20.1 3/4 3/4 3.1 3.4 3/4 0.95 0.2 7
Rev. 1.10
103
September 14, 2009
HT56R67/HT56R668/HT56R678
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright
2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
104
September 14, 2009

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